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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DSP56367 датащи(PDF) 41 Page - Freescale Semiconductor, Inc |
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DSP56367 датащи(HTML) 41 Page - Freescale Semiconductor, Inc |
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41 / 100 page  External Memory Expansion Port (Port A) DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor 3-17 153 RD assertion to data valid tGA 2.5 × TC − 7.0 — 18.0 ns 154 RD deassertion to data not valid6 tGZ 0.0 — ns 155 WR assertion to data active 0.75 × TC − 0.3 7.2 — ns 156 WR deassertion to data high impedance 0.25 × TC —2.5 ns 1 The number of wait states for Page mode access is specified in the DCR. 2 The refresh period is specified in the DCR. 3 The asynchronous delays specified in the expressions are valid for DSP56367. 4 All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., t PC equals 4 × TC for read-after-read or write-after-write sequences). 5 BRW[1:0] (DRAM control register bits) defines the number of wait states that should be inserted in each DRAM out-of page-access. 6 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is t OFF and not tGZ. Table 3-10 DRAM Page Mode Timings, Four Wait States1, 2, 3 No. Characteristics Symbol Expression4 100 MHz Unit Min Max 131 Page mode cycle time for two consecutive accesses of the same direction Page mode cycle time for mixed (read and write) accesses tPC 5 × TC 4.5 × TC 50.0 45.0 — — ns 132 CAS assertion to data valid (read) tCAC 2.75 × TC − 5.7 — 21.8 ns 133 Column address valid to data valid (read) tAA 3.75 × TC − 5.7 — 31.8 ns 134 CAS deassertion to data not valid (read hold time) tOFF 0.0 — ns 135 Last CAS assertion to RAS deassertion tRSH 3.5 × TC − 4.0 31.0 — ns 136 Previous CAS deassertion to RAS deassertion tRHCP 6 × TC − 4.0 56.0 — ns 137 CAS assertion pulse width tCAS 2.5 × TC − 4.0 21.0 — ns 138 Last CAS deassertion to RAS assertion5 • BRW[1–0] = 00, 01—Not applicable • BRW[1–0] = 10 • BRW[1–0] = 11 tCRP — 5.25 × TC − 6.0 7.25 × TC − 6.0 — 46.5 66.5 — — — — ns ns 139 CAS deassertion pulse width tCP 2 × TC − 4.0 16.0 — ns 140 Column address valid to CAS assertion tASC TC − 4.0 6.0 — ns Table 3-9 DRAM Page Mode Timings, Three Wait States1, 2, 3 (continued) No. Characteristics Symbol Expression4 100 MHz Unit Min Max |
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