CSTCC10.0MGA datasheet(47/153 Pages) STMICROELECTRONICS

47 / 153 page

ST72334J/N, ST72314J/N, ST72124J

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MISCELLANEOUS REGISTERS (Cont’d)

13.3 REGISTERS DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1)

Read /Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0]

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]

bits, is applied to the following external interrupts:

ei2 (port B3..0) and ei3 (port B7..4). These 2 bits

can be written only when the I bit of the CC register

is set to 1 (interrupt disabled).

Bit 5 = MCO

Main clock out selection

This bit enables the MCO alternate function on the

I/O port. It is set and cleared by software.

0: MCO alternate function disabled

(I/O pin free for general-purpose I/O)

1: MCO alternate function enabled

(fOSC/2 on I/O port)

Note: To reduce power consumption, the MCO

function is not active in ACTIVE-HALT mode.

Bit 4:3 = IS2[1:0]

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0]

bits, is applied to the following external interrupts:-

ei0 (port A3..0) and ei1 (port F2..0). These 2 bits

can be written only when the I bit of the CC register

is set to 1 (interrupt disabled).

Bit 2:1 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is

applied in the different slow modes. Their action is

conditioned by the setting of the SMS bit. These

two bits are set and cleared by software

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software.

0: Normal mode. fCPU = fOSC / 2

1: Slow mode. fCPU is given by CP1, CP0

See low power consumption mode and MCC

chapters for more details.

IS11

IS10

MCO

IS21

IS20

CP1

CP0

SMS

External Interrupt Sensitivity

IS11 IS10

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

fCPU in SLOW mode

CP1 CP0

fOSC / 4

fOSC / 8

fOSC / 16

fOSC / 32

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