CSTCC10.0MGA datasheet(82/153 Pages) STMICROELECTRONICS

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ST72334J/N, ST72314J/N, ST72124J

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SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.7 Register Description

CONTROL REGISTER (CR)

Read/Write

Reset Value: 0000xxxx (0xh)

Bit 7 = SPIE

Serial peripheral interrupt enable.

This bit is set and cleared by software.

0: Interrupt is inhibited

1: An SPI interrupt is generated whenever SPIF=1

or MODF=1 in the SR register

Bit 6 = SPE

Serial peripheral output enable.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 14.4.4.5 "Master Mode Fault" on

page 79).

0: I/O port connected to pins

1: SPI alternate functions connected to pins

The SPE bit is cleared by reset, so the SPI periph-

eral is not initially connected to the external pins.

Bit 5 = SPR2

Divider Enable.

this bit is set and cleared by software and it is

cleared by reset. It is used with the SPR[1:0] bits to

set the baud rate. Refer to Table 16.

0: Divider by 2 enabled

1: Divider by 2 disabled

Bit 4 = MSTR

Master.

This bit is set and cleared by software. It is also

cleared by hardware when, in master mode, SS=0

(see Section 14.4.4.5 "Master Mode Fault" on

page 79).

0: Slave mode is selected

1: Master mode is selected, the function of the

SCK pin changes from an input to an output and

the functions of the MISO and MOSI pins are re-

versed.

Bit 3 = CPOL

Clock polarity.

This bit is set and cleared by software. This bit de-

termines the steady state of the serial Clock. The

CPOL bit affects both the master and slave

modes.

0: The steady state is a low value at the SCK pin.

1: The steady state is a high value at the SCK pin.

Bit 2 = CPHA

Clock phase.

This bit is set and cleared by software.

0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 1:0 = SPR[1:0]

Serial peripheral rate.

These bits are set and cleared by software.Used

with the SPR2 bit, they select one of six baud rates

to be used as the serial clock when the device is a

master.

These 2 bits have no effect in slave mode.

Table 16. Serial Peripheral Baud Rate

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Serial Clock

SPR2

SPR1

SPR0

fCPU/4

fCPU/8

fCPU/16

fCPU/32

fCPU/64

fCPU/128

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