CSTCC10.0MGA datasheet(74/153 Pages) STMICROELECTRONICS

74 / 153 page

ST72334J/N, ST72314J/N, ST72124J

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SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4 Functional Description

Figure 42 shows the serial peripheral interface

(SPI) block diagram.

This interface contains 3 dedicated registers:

– A Control Register (CR)

– A Status Register (SR)

– A Data Register (DR)

Refer to the CR, SR and DR registers in Section

14.4.7for the bit definitions.

14.4.4.1 Master Configuration

In a master configuration, the serial clock is gener-

ated on the SCK pin.

Procedure

– Select the SPR0 & SPR1 bits to define the se-

rial clock baud rate (see CR register).

– Select the CPOL and CPHA bits to define one

of the four relationships between the data

transfer and the serial clock (see Figure 45).

–The SS pin must be connected to a high level

signal during the complete byte transmit se-

quence.

– The MSTR and SPE bits must be set (they re-

main set only if the SS pin is connected to a

high level signal).

In this configuration the MOSI pin is a data output

and to the MISO pin is a data input.

Transmit sequence

The transmit sequence begins when a byte is writ-

ten the DR register.

The data byte is parallel loaded into the 8-bit shift

and then shifted out serially to the MOSI pin most

significant bit first.

When data transfer is complete:

– The SPIF bit is set by hardware

– An interrupt is generated if the SPIE bit is set

and the I bit in the CCR register is cleared.

During the last clock cycle the SPIF bit is set, a

copy of the data byte received in the shift register

is moved to a buffer. When the DR register is read,

the SPI peripheral returns this buffered value.

Clearing the SPIF bit is performed by the following

software sequence:

1. An access to the SR register while the SPIF bit

is set

2. A read to the DR register.

Note: While the SPIF bit is set, all writes to the DR

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