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UPD78323LP датащи(PDF) 14 Page - Renesas Technology Corp

номер детали UPD78323LP
подробное описание детали  MOS INTEGRATED CIRCUIT
PDF  88 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD78323LP датащи(HTML) 14 Page - Renesas Technology Corp

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12
µPD78323, 78324
RTP0 to RTP7
NMI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
TI
TXD
RXD
SO
SI
SB0
SB1
SCK
AD0 to AD7
1.2
PINS OTHER THAN PORTS (1/2)
A8 to A15
TO00
TO01
TO02
TO03
TO10
TO11
RD
WR
TAS
TMD
WDTO
ASTB
Serial data output of asynchronous serial interface (UART)
Serial data input of asynchronous serial interface (UART)
Serial data output of clock synchronous serial interface in 3-wire mode
Serial data input of clock synchronous serial interface in 3-wire mode
Serial data output of clock synchronous serial interface in SBI mode
Dual-
Function Pin
Function
Pin Name
I/O
Realtime output port which generates pulses in synchronization with the trigger signal
transmitted from the realtime pulse unit (RPU).
Nonmaskable interrupot request input capable of specifying the effective at the rising or
falling edge by a mode register.
Input
Output
P00 to P07
P20
P21
P22
P23
P24
P25
P26
P27/TI
P27/INTP6
P30
P31
P32/SB0
P33/SB1
P32/SO
P33/SI
P34
P40 to P47
P50 to P57
P80
P81
P82
P83
P84
P85
P90
P91
P92
P93
––
––
Input
Input
External count clock input to timer 1 (TM1)
Output
Input
Output
Input
/output
Input
/output
Input
/output
Output
Output
Output
Strobe signal output generated for external memory read operation
Strobe signal output generated for external memory write operation
Control signal output generated for access to turbo access manager
µPD71P301Note
Signal output indicating that the watchdog timer has generated a nonmascable
interrupt.
Timing signal output generated for externally latching the address information output from
pins AD0 to AD7 in order to access the external memory.
Output
Output
External interrupt request input capable of specifying the effective edgy by a mode
register.
Input
Serial clock input/output of clock synchronous serial interface
Multiplexed address/data bus for external memory expansion
Address bus for external memory expansion
Pulse output from the realtime pulse unit
Note
Maintenance product



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