UPD78323LP datasheet(64/88 Pages) RENESAS

номер детали	UPD78323LP

подробное описание детали	MOS INTEGRATED CIRCUIT

PDF	88 Pages

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производитель	RENESAS [Renesas Technology Corp]

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64 / 88 page

µPD78323, 78324

Mnemonic

Operation

Flags

AC P/V CY

Operand

(DE + ) – (HL + ), C

← C–1

End if C=0 or CY=0

(DE – ) – (HL – ), C

← C–1

End if C=0 or CY=0

(DE + ) – A, C

← C–1

End if C=0 or CY=1

(DE – ) – A, C

← C–1

End if C=0 or CY=1

(DE + ) – (HL + ), C

← C–1

End if C=0 or CY=1

(DE – ) – (HL – ), C

← C–1

End if C=0 or CY=1

STBC

← byteNote

WDM

← byteNote

RSS

← RSS

RBS2 – 0

← n, RSS ← 0

RBS2 – 0

← n, RSS ← 1

No Operation

← 1 (Enable Interrupt)

← 0 (Disable Interrupt)

[DE – ], A

[DE + ], [HL + ]

[DE – ], [HL – ]

STBC, #byte

WDM, #byte

RBn

RBn, ALT

[DE + ], [HL + ]

[DE – ], [HL – ]

[DE + ], A

CMPBKC

CMPMNC

CMPBKNC

MOV

SWRS

SEL

NOP

×××

××

Note

If the operation code of STBC register and WDM register operation instructions is abnormal, an operation code

trap interrupt is generated.

Operation in the eent of trap:

(SP–1)

← PSWH, (SP–2) ← PSWL,

(SP–3)

← (PC–4)H, (SP–4) ← (PC–4)L,

PCL

← (003CH), PCH ← (003DH),

← SP–4, IE ← 0

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