UPD161401WSLASHP datasheet(21/126 Pages) RENESAS

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Data Sheet S15726EJ2V0DS

µµµµPD161401

5.1.3 Serial interface

When the serial interface has been selected (IFM1, IFM0 = L, L), as long as the chip is in an active state (/CS1= L,

CS2 = H ), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read in the order of D7, then

D6 to D0 at the rising edge of the serial clock input from the serial input pin. This data is converted to parallel data in

synchronization with the 8th rising edge of the serial clock. Serial input data is judged as display data/command data if

RS = H and an index if RS = L. The RS input is read every 8th rising edge of the serial clock after the chip becomes

active and is used for data discrimination.

Figure 5

−−−−1. Serial Interface Signal Chart

123456789

/CS1

SCL

CS2 = "H"

Remarks 1. If the chip is not in an active state, the shift register and counter are reset to their initial statuses.

2. The serial clock counter is reset by initialization from the /DISP pin.

3. Data cannot be read when using serial interface mode.

4. Care must be taken when performing SCL wiring to avoid effects from terminal radiation or external noise

caused by the wiring length. It is recommended to confirm operation using the actual equipment to be

used.

5.1.4 Chip select

The

µPD161401 has chip select pins (/CS1 and CS2). The CPU parallel interface or Serial interface can be used only

when /CS1 = L (CS2 = H).

If the chip select pins are not active, the D0 to D15 pins go into a high-impedance state, and the RS, /RD, and /WR pins

do not become active.

5.1.5 Accessing display data RAM and internal registers

When the CPU accesses the

µPD161401, the CPU only has to satisfy the requirement of the cycle time (tCYC) and can

transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration.

When the CPU writes data to the

µPD161401, no dummy data is necessary. When reading data, dummy data is not

necessary either. In the

µPD161401, the data of the display access memory register, the complementary color blink

data memory register, the specified color blink data memory register and the reverse data memory access register

(R12, R41, R45, R50) cannot be read. Figure 5

−−−−2 illustrates as follows.

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