UPD161401WSLASHP datasheet(66/126 Pages) RENESAS

66 / 126 page

Data Sheet S15726EJ2V0DS

µµµµPD161401

6.1 Control Register 1 (R0)

This command specifies the general operation mode of the

µPD161401.

E /RD

R,/W

/WR

TRON

WAS

COMF

DISP

STBY

HALT

ADC

COMR

TRON

0: Normal mode (all values written to the test register are ignored)

1: Test register valid mode (values written to the test register are valid)

WAS

0: Normal data write mode

1: Window access mode (Refer to 5.2.7 Arbitrary address area access (window access mode (WAS)).)

COMF

0: Normal display operation

1: All output from common pins is OFF (all the common pins output a non-selected waveform. At this time, the

segment pins output OFF data (level 0)).

DISP

0: Display OFF (All the LCD output pins output a VSS level, and the oscillator and DC/DC converter operate.)

1: Display ON

STBY

0: Normal operation

1: Internal operation and oscillation stop. Display OFF

HALT

0: Internal operation starts.

1: Internal operation stops (all the LCD output pins output a VSS level, the oscillator operates, and the DC/DC

converter stops, and the reference voltage generator operates).

ADC

Column addresses correspond to SEG outputs that are used to display the display data RAM (refer to Table 6

−−−−1).

COMR

Selects the direction in which the lines of the graphic RAM are read (refer to Table 6

−−−−2).

Table 6

−−−−1. Relationship between Column Address of Display RAM and Segment Output

SEG Output

SEG1

• • •

SEG303

000H

→

Column address

→

12EH

ADC

(D1)

12EH

←

Column address

←

000H

Table 6

−−−−2. Relationship between Common Scan Circuit and Scan Direction

00H

→

4FH

COMR

(D0)

14FH

→

00H

Default (default value of reset command)

00000000

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