APEX20K datasheet(40/117 Pages) ALTERA

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Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

APEX 20KE devices include an enhanced IOE, which drives the FastRow

interconnect. The FastRow interconnect connects a column I/O pin

directly to the LAB local interconnect within two MegaLAB structures.

This feature provides fast setup times for pins that drive high fan-outs

with complex logic, such as PCI designs. For fast bidirectional I/O timing,

LE registers using local routing can improve setup times and OE timing.

The APEX 20KE IOE also includes direct support for open-drain

operation, giving faster clock-to-output for open-drain signals. Some

programmable delays in the APEX 20KE IOE offer multiple levels of delay

to fine-tune setup and hold time requirements. The Quartus II software

compiler can set these delays automatically to minimize setup time while

providing a zero hold time.

Table 11 describes the APEX 20KE programmable delays and their logic

options in the Quartus II software.

The register in the APEX 20KE IOE can be programmed to power-up high

or low after configuration is complete. If it is programmed to power-up

low, an asynchronous clear can control the register. If it is programmed to

power-up high, an asynchronous preset can control the register. Figure 26

shows how fast bidirectional I/O pins are implemented in APEX 20KE

devices. This feature is useful for cases where the APEX 20KE device

controls an active-low input or another device; it prevents inadvertent

activation of the input upon power-up.

Table 11. APEX 20KE Programmable Delay Chains

Programmable Delays

Quartus II Logic Option

Input Pin to Core Delay

Decrease input delay to internal cells

Input Pin to Input Register Delay

Decrease input delay to input registers

Core to Output Register Delay

Decrease input delay to output register

Output Register tCO Delay

Increase delay to output pin

Clock Enable Delay

Increase clock enable delay

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