APEX20K datasheet(32/117 Pages) ALTERA

номер детали	APEX20K

подробное описание детали	Programmable Logic Device Family

PDF	117 Pages

Scroll/Zoom	100%

производитель	ALTERA [Altera Corporation]

домашняя страница	http://www.altera.com

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32 / 117 page

Altera Corporation

APEX 20K Programmable Logic Device Family Data Sheet

Read/Write Clock Mode

The read/write clock mode contains two clocks. One clock controls all

registers associated with writing: data input, WE, and write address. The

other clock controls all registers associated with reading: read enable

(RE), read address, and data output. The ESB also supports clock enable

and asynchronous clear signals; these signals also control the read and

write registers independently. Read/write clock mode is commonly used

for applications where reads and writes occur at different system

frequencies. Figure 20 shows the ESB in read/write clock mode.

Figure 20. ESB in Read/Write Clock Mode

Note (1)

Notes to Figure 20:

(1)

All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.

(2)

APEX 20KE devices have four dedicated clocks.

Dedicated Clocks

2 or 4

ENA

data[ ]

rdaddress[ ]

wraddress[ ]

RAM/ROM

128

× 16

256

× 8

512

× 4

1,024

× 2

2,048

× 1

Data In

Read Address

Write Address

Read Enable

Write Enable

Data Out

outclocken

inclocken

inclock

outclock

ENA

Write

Pulse

Generator

rden

wren

Dedicated Inputs &

Global Signals

To MegaLAB,

FastTrack &

Local

Interconnect

(2)

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