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APEX20K датащи(PDF) 39 Page - Altera Corporation

номер детали APEX20K
подробное описание детали  Programmable Logic Device Family
PDF  117 Pages
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производитель  ALTERA [Altera Corporation]
домашняя страница  http://www.altera.com
Logo ALTERA - Altera Corporation

APEX20K датащи(HTML) 39 Page - Altera Corporation

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Altera Corporation
39
APEX 20K Programmable Logic Device Family Data Sheet
Figure 25. APEX 20K Bidirectional I/O Registers
Note (1)
Note to Figure 25:
(1)
The output enable and input registers are LE registers in the LAB adjacent to the bidirectional pin.
VCC
OE[7..0]
CLK[1..0]
ENA[5..0]
CLRn[1..0]
Peripheral Control
Bus
CLRN
D
Q
ENA
VCC
2 Dedicated
Clock Inputs
Chip-Wide
Output Enable
CLK[3..2]
2
12
VCC
VCC
Chip-Wide
Reset
Input Pin to
Core Delay
Slew-Rate
Control
VCCIO
Optional
PCI Clamp
Output Register
t
Delay
Core to Output
Register Delay
Input Pin to Input
Register Delay
CLRN
DQ
ENA
VCC
Chip-Wide
Reset
Input Register
Output Register
CLRN
DQ
ENA
Chip-Wide Reset
VCC
OE Register
VCC
4 Dedicated
Inputs
Row, Column,
or Local Interconnect
CO
Open-Drain
Output



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