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CC1021-RTR1 датащи(PDF) 14 Page - Texas Instruments |
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CC1021-RTR1 датащи(HTML) 14 Page - Texas Instruments |
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14 / 92 page ![]() CC1021 SWRS045 Page 14 of 91 4.7. Digital Inputs / Outputs Parameter Min Typ Max Unit Condition / Note Logic "0" input voltage 0 0.3* VDD V Logic "1" input voltage 0.7* VDD VDD V Logic "0" output voltage 0 0.4 V Output current 2.0 mA, 3.0 V supply voltage Logic "1" output voltage 2.5 VDD V Output current 2.0 mA, 3.0 V supply voltage Logic "0" input current NA 1 µA Input signal equals GND. PSEL has an internal pull-up resistor and during configuration the current will be -350 µA. Logic "1" input current NA 1 µA Input signal equals VDD DIO setup time 20 ns TX mode, minimum time DIO must be ready before the positive edge of DCLK. Data should be set up on the negative edge of DCLK. DIO hold time 10 ns TX mode, minimum time DIO must be held after the positive edge of DCLK. Data should be set up on the negative edge of DCLK. Serial interface (PCLK, PDI, PDO and PSEL) timing specification See Table 14 on page 24 for more details Pin drive, LNA_EN, PA_EN 0.90 0.87 0.81 0.69 0.93 0.92 0.89 0.79 mA mA mA mA mA mA mA mA Source current 0 V on LNA_EN, PA_EN pins 0.5 V on LNA_EN, PA_EN pins 1.0 V on LNA_EN, PA_EN pins 1.5 V on LNA_EN, PA_EN pins Sink current 3.0 V on LNA_EN, PA_EN pins 2.5 V on LNA_EN, PA_EN pins 2.0 V on LNA_EN, PA_EN pins 1.5 V on LNA_EN, PA_EN pins See Figure 35 on page 61 for more details. Table 9. Digital inputs / outputs parameters |
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