CC1021-RTR1 datasheet(13/92 Pages) TI

13 / 92 page

CC1021

SWRS045

Page 13 of 91

4.6.

Frequency Synthesizer Section

Parameter

Min

Typ

Max

Unit

Condition / Note

Phase noise, 402 ñ 470 MHz

-79

-80

-87

-100

-105

dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 13.

The phase noise will be higher for

larger PLL loop filter bandwidth.

Phase noise, 804 ñ 940 MHz

-73

-74

-81

-94

-111

dBc/Hz

Unmodulated carrier

At 12.5 kHz offset from carrier

At 25 kHz offset from carrier

At 50 kHz offset from carrier

At 100 kHz offset from carrier

At 1 MHz offset from carrier

Measured using loop filter

components given in Table 13.

The phase noise will be higher for

larger PLL loop filter bandwidth.

PLL loop filter bandwidth

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

30.5

kHz

After PLL and VCO calibration.

The PLL loop bandwidth is

programmable.

See Table 25 on page 52 for loop

filter component values.

PLL lock time (RX / TX turn time)

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

Loop filter 5, up to 153.6 kBaud

140

307.2 kHz frequency step to RF

frequency within ±10 kHz, ±15

kHz, ±50 kHz settling accuracy

for loop filter 2, 3 and 5

respectively. Depends on loop

filter component values and

PLL_BW register setting. See

Table 26 on page 53 for more

details.

PLL turn-on time. From power down

mode with crystal oscillator running.

Loop filter 2, up to 19.2 kBaud

Loop filter 3, up to 38.4 kBaud

Loop filter 5, up to 153.6 kBaud

1300

1080

700

Time from writing to registers to

RF frequency within ±10 kHz, ±15

kHz, ±50 kHz settling accuracy

for loop filter 2, 3 and 5

respectively. Depends on loop

filter component values and

PLL_BW register setting. See

Table 25 on page 53 for more

details.

Table 8. Frequency synthesizer parameters

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