UPD78P324LP datasheet(49/82 Pages) RENESAS

номер детали	UPD78P324LP

подробное описание детали	MOS INTEGRATED CIRCUIT

PDF	82 Pages

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производитель	RENESAS [Renesas Technology Corp]

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µPD78P324, 78P324(A)

(3)

µPD78P324(A1) Electrical Specifications (7/9)

Serial Operation (TA = –40 to +110

°C, VDD = +5 V ±10 %, VSS = 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCK output

Internal divide-by-eight

1280

µs

Serial clock cycle time

tCYSK

SCK input

External clock

1280

µs

SCK output

Internal divide-by-eight

560

Serial clock low-level width

tWSKL

SCK input

External clock

560

SCK output

Internal divide-by-eight

560

Serial clock high-level width

tWSKH

SCK input

External clock

560

SI setup time (vs. SCK

↑)tSRXSK

SI hold time (vs. SCK

↑)tHSKRX

SCK

↓ → SO delay time

tDSKTX

R = 1 k

Ω , C = 100pF

210

tCYK-dependent Serial Operation

Symbol

Condition

Calculation Formula

MIN./MAX.

Unit

SCK output

Internal divide-by-eight

MIN.

tCYSK

SCK input

External clock

MIN.

SCK output

Internal divide-by-eight

4T–80

MIN.

tWSKL

SCK input

External clock

4T–80

MIN.

SCK output

Internal divide-by-eight

4T–80

MIN.

tWSKH

SCK input

External clock

4T–80

MIN.

Remarks

1. T = tCYK = 1/fCLK (fCLK refers to the internal system clock frequency)

2. Among the parameters for serial operation, only those listed in this table are dependent on tCYK.

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