UPD78P324LP datasheet(33/82 Pages) RENESAS

33 / 82 page

µPD78P324, 78P324(A)

(1)

µPD78P324 Electrical Specifications (9/9)

AC Timing Test Point

A/D Converter Characteristics (TA = –10 to +70

°C, VDD = +5 V ±10 %, VSS = AVSS = 0 V, VDD –0.5 V ≤ AVDD ≤ VDD)

Parameter

Resolution

Total errorNote1

Quantization error

Conversion time

Sampling time

Zero-scale errorNote1

Full-scale errorNote 1

Non-linear errorNote 1

Analog input voltageNote 2

Analog input impedance

Reference voltage

AVREF current

AVDD supply current

A/D converter data retention current

MIN.

TYP.

MAX.

Unit

bit

±0.4

%FSR

±0.7

%FSR

±1/2

LSB

144

tCYK

±1.5

±2.5

LSB

±1.5

±4.5

LSB

±1.5

±2.5

LSB

±1.5

±4.5

LSB

±1.5

±2.5

LSB

±1.5

±4.5

LSB

0AVDD

Ω

Note 3

3.4

AVDD

1.0

3.0

2.0

6.0

215

µA

Symbol

tCONV

tSAMP

VIAN

RAN

AVREF

AIREF

AIDD

AIDDDR

Condition

4.5 V

≤ AVREF ≤ AVDD

3.5 V

≤ AVREF ≤ AVDD

4.5 V

≤ AVREF ≤ AVDD

3.4 V

≤ AVREF ≤ AVDD

4.5 V

≤ AVREF ≤ AVDD

3.4 V

≤ AVREF ≤ AVDD

4.5 V

≤ AVREF ≤ AVDD

3.4 V

≤ AVREF ≤ AVDD

When not sampled

When sampled

Operation mode

AVDDDR = 2.5 V

STOP mode

AVDDDR=5 V

±10%

Notes 1. Quantization error excluded.

2. When –0.3 V

≤ VIAN ≤ 0 V, the conversion result becomes 000H.

When 0 V < VIAN < AVREF, the conversion is performed at a resolution of 10 bits.

When AVREF

≤ VIAN ≤ AVDD, the conversion result is 3FFH.

3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram

below. (The values in the diagram are TYP. values; therefore, they are not assured.)

0.8VDD or 2.2V

0.8V

0.8VDD or 2.2V

0.8V

Test point

VDD

20k

Ω

10pF

30pF

Analog input pin

( input

capacitance

included )

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