M58BW16F datasheet(27/81 Pages) STMICROELECTRONICS

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M58BW16F, M58BW32F

Bus operations

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3.2

Synchronous bus operations

For synchronous bus operations refer to Table 7 together with the following text. The read

access will start at whichever of the three following events occurs last: valid address

transition, Chip Enable, E, going Low, VIL or Latch Enable, L, going Low, VIL.

3.2.1

Synchronous Burst Read

Synchronous Burst Read operations are used to read from the memory at specific times

synchronized to an external reference clock. The valid edge of the Clock signal is the rising

edge. Once the Flash memory is configured in Burst mode, it is mandatory to have an active

clock signal since the switching of the output buffer databus is synchronized to the rising

edge of the clock. In the absence of clock, no data is output.

The burst type, length and latency can be configured. The different configurations for

Synchronous Burst Read operations are described in the Burst Configuration Register

section. Refer to Figure 4 for examples of synchronous burst operations.

A valid Synchronous Burst Read operation begins when the Burst Clock is active and Chip

Enable and Latch Enable are Low, VIL. The burst start address is latched and loaded into

the internal Burst Address Counter on the valid Burst Clock K edge or on the rising edge of

Latch Enable, whichever occurs first.

After an initial memory latency time, the memory outputs data each clock cycle. The Burst

Address Advance B input controls the memory burst output. The second burst output is on

the next clock valid edge after the Burst Address Advance B has been pulled Low.

Valid Data Ready, R, monitors if the memory burst boundary is exceeded and the Burst

Controller of the microprocessor needs to insert wait states. When Valid Data Ready is Low

on the rising clock edge, no new data is available and the memory does not increment the

internal address counter at the active clock edge even if Burst Address Advance, B, is Low.

Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid

immediately at the rising clock edge.

Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH.

If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid.

If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address

Advance, B, is at VIL the internal Burst Address Counter is incremented at each Burst Clock

K rising edge.

The Synchronous Burst Read timing diagrams and AC Characteristics are described in the

AC and DC Parameters section. See Figures 14, 17, 18 and 19, and Table 21.

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