Philips Semiconductors

PCF85116-3

2048

Product data

Rev. 04 — 25 October 2004

12 of 21

9397 750 14217

© Koninklijke Philips Electronics N.V. 2004. All rights reserved.

[1]

The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by

a transmitter.

[2]

Table 8:

Symbol

Parameter

Conditions

Standard mode

Fast mode

Unit

Min

Max

Min

Max

clock frequency

0

100

0

400

kHz

time the bus must be free before

new transmission can start

4.7

-

1.3

-

µs

START condition hold time after

which first clock pulse is generated

4.0

-

0.6

-

µs

LOW level clock period

4.7

-

1.3

-

µs

HIGH level clock period

4.0

-

0.6

-

µs

set-up time for START condition

repeated start

4.7

-

0.6

-

µs

data hold time

for CBUS compatible masters

5

-

-

-

µs

[1]

0-

0

-

ns

data set-up time

250

-

100

-

ns

SDA and SCL rise time

-

1000

20 + 0.1Cb[2] 300

µs

SDA and SCL fall time

-

300

20 + 0.1Cb[2] 300

ns

set-up time for STOP condition

4.0

-

0.6

-

µs

P = STOP condition; S = START condition.

Fig 9.

MBA705

t BUF

HD;STA

t

SCL

SDA

P

S

t LOW

t r

HD;DAT

t

SU;DAT

t

t f

t HIGH

S

HD;STA

t

SU;STA

t

SU;STO

t

P