CS5535 datasheet(119/555 Pages) NSC

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SMB Controller Functional Description (Continued)

4.10.1.5 Arbitration on the Bus

Multiple master devices on the bus require arbitration

between their conflicting bus SMB demands. Control of the

bus is initially determined according to address bits and

clock cycle. If the masters are trying to address the same

slave, data comparisons determine the outcome of this

arbitration. In master mode, the device immediately aborts

a transaction if the value sampled on the SDA line differs

from the value driven by the device. (An exception to this

rule is SDA while receiving data. The lines may be driven

low by the slave without causing an abort.)

The SCL signal is monitored for clock synchronization and

to allow the slave to stall the bus. The actual clock period is

set by the master with the longest clock period, or by the

slave stall period. The clock high period is determined by

the master with the shortest clock high period.

When an abort occurs during the address transmission, a

master that identifies the conflict should give up the bus,

switch to slave mode, and continue to sample SDA to

check if it is being addressed by the winning master on the

bus.

4.10.1.6 Master Mode

This discussion and Section 4.10.1.7 "Slave Mode" refer-

ence several bits in the SMB Native register set (e.g.,

SMBCTL1.STASTRE, SMBST.MASTER, etc.). Table 4-18

provides the bit map for the SMB Native registers for the

reader’s convenience. For full bit descriptions, refer to Sec-

tion 5.11.1 "SMB Native Registers" on page 354.

Requesting Bus Mastership

An SMB transaction starts with a master device requesting

bus mastership. It asserts a START condition, followed by

the address of the device that wants the bus. If this transac-

tion is successfully completed, the software may assume

that the device has become the bus master.

For the device to become the bus master, the software

should perform the following steps:

Configure SMBCTL1.INTEN to the desired operation

mode (Polling = 0 or Interrupt = 1) and set

SMBCTL1.START. This causes the SMB Controller to

issue a START condition on the bus when the bus

becomes free (SMBCST.BB is cleared, or other condi-

tions that can delay START). It then stalls the bus by

holding SCL low.

If a bus conflict is detected (i.e., another device pulls

down the SCL signal), SMBST.BER is set.

If there is no bus conflict, SMBST.SDAST and

SMBST.MASTER are set.

If SMBCTL1.INTEN is set and either SMBST.BER or

SMBST.SDAST is set, an interrupt is issued.

Sending the Address Byte

When the device is the active master of the bus

(SMBST.MASTER is set), it can send the address on the

bus.

The address sent should not be the device’s own address,

as defined by the ADDR bits of the SMBADDR register if

the SMBADDR.SAEN is set, nor should it be the global call

address if the SMBCST.GCMTCH is set.

To send the address byte, use the following sequence:

For a receive transaction, where the software wants

only one byte of data, it should set SMBCTL1.ACK. If

only an address needs to be sent or if the device

requires

stall

for

some

other

reason,

set

the

SMBCTL1.STASTRE.

Write the address byte (7-bit target device address)

and the direction bit to SMBSDA. This causes the

SMB Controller to generate a transaction. At the end

of this transaction, the acknowledge bit received is

copied to SMBST.NEGACK. During the transaction,

the SDA and SCL lines are continuously checked for

conflict with other devices. If a conflict is detected, the

transaction is aborted, SMBST.BER is set, and

SMBST.MASTER is cleared.

Table 4-18. SMB Native Registers Map

SMB I/O

Offset

Name

7654321

00h

SMBSDA

01h

SMBST

SLVSTP

SDAST

BER

NEGACK

STASTR

NMATCH

MASTER

XMIT

02h

SMBCST

RSVD

TGSCL

TSDA

GCMTCH

MATCH

BUSY

03h

SMBCTL1

STASTRE

NMINTE

GCMEN

ACK

RSVD

INTEN

STOP

START

04h

SMBADDR

SAEN

SMBADDR

05h

SMBCTL2

SCLFRQ

06h

SMBCTL3

SCLFRQ

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