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CS5535 датащи(PDF) 106 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 106 Page - National Semiconductor (TI) |
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106 / 555 page ![]() www.national.com 106 Revision 0.8 PIC Functional Description (Continued) As illustrated in Figure 4-20, the blocks that make up the 8259A PIC are: • Read/Write Control Logic • Interrupt Request Register (IRR) • In-Service Register (ISR) • Interrupt Mask Register (IMR) • Priority Resolver • Interrupt Sequence • Data Bus Buffer • Cascade Buffer/Comparator Read/Write Control Logic The function of this block is to accept commands from the CPU. It contains the four Initialization Command Word reg- isters, ICW1-ICW4, and three Operation Command Word registers, OCW1-OCW3, that can be programmed to oper- ate in various modes. IRR, ISR, and IMR Three registers are available to handle interrupts in the PIC: Interrupt Request Register (IRR), In-Service Register (ISR), and Interrupt Mask Register (IMR). Each of the three registers is eight bits wide, where every bit corresponds to one of the IR0-IR7 input lines. Priority Resolver The priority resolver block manages the hardware requests according to their priority. As several bits may be set in the IRR simultaneously, the priority encoder passes only the highest priority bit; ordered in priority 0 through 7 (0 being the highest). Interrupt Sequence The INT output goes directly to the CPU interrupt input. When an INT signal is activated, the CPU responds with an Interrupt Acknowledge access that is translated to two pulses on the INTA input of the PIC. At the first INTA pulse the highest priority IRR bit is loaded into the corresponding ISR bit, and that IRR bit is reset. The second INTA pulse instructs the PIC to present the 8-bit vector of the interrupt handler onto the data bus. Data Bus Buffer Control words and status information are transferred through the data bus buffer. Cascade Buffer/Comparator This functional block stores and compares the IDs of the PICs. Figure 4-20. PIC 8259A Block Diagram Internal Bus Interrupt Mask Register (IMR) In-Service Register (ISR) Priority Resolver Interrupt Request Register (IRR) Control Logic Data Bus Buffer Read/ Write Logic Cascade Buffer/ Comparator INTA INT D7-D0 RD WR A0 CS CAS0 CAS1 CAS2 SP/EN IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7 |
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