CS5535 datasheet(532/555 Pages) NSC

532 / 555 page

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532

Revision 0.8

Electrical Specifications (Continued)

6.3.1

Clock Inputs

All of the clocks in Table 6-7 indicate a minimum frequency

of zero. Specifically, there are no dynamic circuits with min-

imum clock speeds. Additionally, Active Hardware Clock

Gating (AHCG) (see Section 3.9 "Power Management" on

page 72) will turn off all or some of the system clocks at

selected

points

time

save

power.

The

KHZ32_XCI/KH32XCO being the one exception to “off all”.

It always runs.

While the above discussion is accurate, there are minimum

clock requirements for proper system operation. These are

indicated in the Notes for each clock in Table 6-7.

Table 6-7. Clock Timing Parameters

Signal

Parameter

Min

Typ

Max

Units

Comment/Condition

MHZ66_CLK

Frequency

66.00

66.50

MHz

Note 1 and Note 2.

Rise/Fall Time

0.5

High/Low Time

None

Note 3.

PCI_CLK

Frequency

33 or 66

67.50

MHz

Note 1 and Note 4.

Rise/Fall Time

0.5

High/Low Time

None

Note 3.

MHZ48_CLK

Frequency

48.00

49.25

MHz

Note 1 and Note 5.

Rise/Fall Time

0.5

High/Low Time

None

Note 3.

LPC_CLK

Frequency

MHz

Note 1, Note 4, and Note 6.

Rise/Fall Time

0.5

High/Low Time

None

Note 3.

MHZ14_CLK

Frequency

14.31818

15.00

MHz

Note 1 and Note 7.

Rise/Fall Time

0.5

High/Low Time

None

Note 3.

AC_CLK

Frequency

12.239

13.00

MHz

Note 1 and Note 8.

Rise/Fall Time

0.5

High/Low Time

None

Note 3.

TCK

Frequency

4.0

15.00

MHz

Note 1.

Rise/Fall Time

0.5

High/Low Time

None

Note 3.

KHZ32_XCI

KHZ32_XCO

Frequency

32.768

1000

kHz

Note 1 and Note 9.

High/Low Time

0.5

None

µs

Note 3.

Note 1. Signal parameters are defined in Figure 6-1 "Clock Reference Definition" on page 530.

Note 2. Operationally, the minimum clock is 64.50 MHz. Operation out of the 66 MHz range indicated causes the CS5535

ATA Controller to operate out of ATA specification limits.

Note 3. Clock duty cycles not 100% tested. Guaranteed by design.

Note 4. For maximum system performance, this clock should be as high as possible up to the maximum indicated.

Note 5. The USB spec requires a controller accuracy of +/- 0.05% (500 ppm).

Note 6. Must be greater than half the MHZ14_CLK frequency.

Must be at least four times faster than the KHZ32_XCI frequency.

Note 7. This clock is used as the system time base and hence should have the “typical” frequency indicated.

Note 8. This clock should be connected to the external codec output that is half the codec input clock of 24.478 MHz.

Note 9. Typically, connect these pins to a 32.768 kHz crystal. However, an external oscillator may be connected to the

KHZ32_XCI pin and driven to the maximum rate shown for testing. When operated with an external oscillator, leave

the KHZ32_XCO pin open. When operating with an external oscillator, input voltage on KHZ32_XCI (khz32_xci)

should swing rail-to-rail, that is, zero-to-VIO_VSB. With external oscillator, the input voltage high should always be

at least 3.0 volts.

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