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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS5535 датащи(PDF) 353 Page - National Semiconductor (TI) |
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CS5535 датащи(HTML) 353 Page - National Semiconductor (TI) |
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353 / 555 page  Revision 0.8 353 www.national.com 5.11 SYSTEM MANAGEMENT BUS REGISTER DESCRIPTIONS The registers for the System Management Bus (SMB) are divided into two sets: • Standard GeodeLink Device MSRs (Shared with DIVIL, see Section 5.6.1 on page 299.) • SMB Native Registers The MSRs are accessed via the RDMSR and WRMSR pro- cessor instructions. The MSR address is derived from the perspective of the CPU Core. See Section 3.2 "CS5535 MSR Addressing" on page 53 for more details on MSR addressing. The Native registers (summarized in Table 5-27) are accessed via Base Address Register MSR_LBAR_SMB (MSR 5140000Bh) as I/O Offsets. (See Section 5.6.2.4 on page 309 for bit descriptions of the Base Address Regis- ter.) The reference column in the summary table points to the page where the register maps and bit descriptions are listed. Table 5-27. SMB Native Registers Summary SMB I/O Offset Type Width (Bits) Register Name Reset Value Reference 00h R/W 8 SMB Serial Data (SMB_SDA) 00h Page 354 01h R/W 8 SMB Status (SMB_STS) 00h Page 354 02h R/W 8 SMB Control Status (SMB_CTRL_STS) 10h Page 356 03h R/W 8 SMB Control 1 (SMB_CTRL1) 00h Page 357 04h R/W 8 SMB Address (SMB_ADDR) 00h Page 358 05h R/W 8 SMB Control 2 (SMB_CTRL2) 00h Page 359 06h R/W 8 SMB Control 3 (SMB_CTRL3) 00h Page 359 07h R/W 8 SMB Reserved Register (SMBRSVD). Writes are “don't care” and reads return undefined value. xxh --- |
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