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CS5535 датащи(PDF) 308 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали CS5535
подробное описание детали  Geode??CS5535 I/O Companion Multi-Function South Bridge
PDF  555 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
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CS5535 датащи(HTML) 308 Page - National Semiconductor (TI)

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308
Revision 0.8
DIVIL Register Descriptions (Continued)
5.6.2.2
Local BAR - KEL from USB Host Controller 1 (DIVIL_LBAR_KEL1)
See Section 4.6.1 "LBARs and Comparators" on page 97 for operational details.
The KEL registers take 4 kB of memory space. However, only offsets 100h, 104h, 108h, and 10Ch contain registers. All
other writes are “don’t care” and reads return 0.
This is one of two KEL LBARs. Each LBAR “hits” to the same KEL. This allows USB Host Controllers at different addresses
to be used, if desired. Both LBARs do NOT have to be used.
5.6.2.3
Local BAR - KEL from USB Host Controller 2 (DIVIL_LBAR_KEL2)
See Section 4.6.1 "LBARs and Comparators" on page 97 for operational details.
The KEL registers take 4 kB of memory space. However, only offsets 100h, 104h, 108h, and 10Ch contain registers. All
other writes are “don’t care” and reads return 0.
This is one of two KEL LBARs. Each LBAR "hits" to the same KEL. This allows USB Host Controllers at different addresses
to be used if desired. Both LBARs do NOT have to be used.
15:5
BASE_ADDR
Base Address in I/O Space. See discussion in Section 4.6.1 "LBARs and Compara-
tors" on page 97.
4:0
RSVD
Reserved. Reads return 0; writes have no effect.
MSR Address
51400009h
Type
R/W
Reset Value
00000000_00000000h
DIVIL_LBAR_KEL1 Register Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
MEM_MASK
RSVD
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
87654321
0
BASE_ADDR
RSVD
DIVIL_LBAR_KEL1 Bit Descriptions
Bit
Name
Description
63:44
MEM_MASK
Memory Address Mask Value. See discussion in Section 4.6.1 "LBARs and Compar-
ators" on page 97
43:33
RSVD
Reserved. Reads return 0; writes have no effect.
32
LBAR_EN
LBAR Enable.
0: Disable LBAR.
1: Enable LBAR.
31:12
BASE_ADDR
Base Address in Memory Space. See discussion in Section 4.6.1 "LBARs and Com-
parators" on page 97
11:0
RSVD
Reserved. Reads return 0; writes have no effect.
MSR Address
5140000Ah
Type
R/W
Reset Value
00000000_00000000h
DIVIL_MSR_LBAR_IRQ Bit Descriptions
Bit
Name
Description



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