CS5535 datasheet(230/555 Pages) NSC

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5.3

AC97 AUDIO CODEC CONTROLLER REGISTER DESCRIPTIONS

The control registers for the AC97 Audio Codec Controller

(ACC) are divided into two register sets:

• Standard GeodeLink Device MSRs

• ACC Native Registers

The MSRs are accessed via the RDMSR and WRMSR pro-

cessor instructions. The MSR address is derived from the

perspective of the CPU Core. See Section 3.2 "CS5535

MSR Addressing" on page 53 for more details on MSR

addressing.

The ACC Native registers begin at ACC Offset 00h. The

system automatically maps the ACC registers to a location

in memory space or I/O space, but this is hidden from the

module’s point of view. At the audio block level, it does not

matter if these registers are in memory or I/O space but at

the system level, there are significant operational differ-

ences (see Section "Eliminating Race Conditions") Hereaf-

ter the ACC Address are called out as I/O Offsets, since I/O

mapping is recommended.

For Native register access, only the lower seven bits of the

address are decoded, so the register space is aliased.

Accesses beyond 7Fh alias below 7Fh. Accesses to

addresses that are not implemented or reserved are “don’t

cares” (i.e. writes do nothing, reads return 0s).

Tables 5-8 and 5-9 are ACC register summary tables that

include reset values and page references where the bit

descriptions are provided.

Eliminating Race Conditions

All I/O writes are sequence locked, that is, completion of

the write at the target is confirmed before the executing

processor proceeds to the next instruction. All memory

writes are posted, that is, the executing processor pro-

ceeds to the next instruction immediately after the write

whether or not the write has completed. Write posting can

lead to out of order execution. Reading the register to

which a write has been posted, forces any pending posted

write to execute if it has not already done so.

Consider this example. Assume an audio master is per-

forming an access to system memory and register access

is temporarily blocked. If the processor was servicing an

interrupt, a write to clear the interrupt would post to a mem-

ory mapped register but not execute immediately, that is,

the interrupt would not immediately clear. If the processor

then enabled the Programmable Interrupt Controller (PIC)

for new interrupts, then the “not immediately cleared” inter-

rupt would cause a false new interrupt, a form of a race

condition.

This type of race condition can be eliminated by placing the

audio registers in I/O space, or, by performing a register

read to any register having a pending posted write that is

capable of creating a race condition.

Table 5-8. Standard GeodeLink Device MSRs Summary

MSR Address

Type

Reset Value

Reference

51500000h

GeodeLink Device Capabilities MSR

(ACC_GLD_MSR_CAP)

00000000_002330xxh

Page 233

51500001h

R/W

GeodeLink Device Master Configuration MSR

(ACC_GLD_MSR_CONFIG)

00000000_0000F000h

Page 233

51500002h

R/W

GeodeLink Device SMI MSR

(ACC_GLD_MSR_SMI)

00000000_00000000h

Page 234

51500003h

R/W

GeodeLink Device Error MSR

(ACC_GLD_MSR_ERROR)

00000000_00000000h

Page 235

51500004h

R/W

GeodeLink Device Power Management MSR

(ACC_GLD_MSR_PM)

00000000_00000000h

Page 236

51500005h

R/W

GeodeLink Device Diagnostic MSR

(ACC_GLD_MSR_DIAG)

00000000_00000000h

Page 236

Table 5-9. ACC Native Registers Summary

ACC I/O Offset

Type

Width

(Bits)

Name

Reset Value

Reference

00h

R/W

Codec GPIO Status Register

(ACC_GPIO_STATUS)

00000000h

Page 236

04h

R/W

Codec GPIO Control Register

(ACC_GPIO_CNTL)

00000000h

Page 237

08h

R/W

Codec Status Register

(ACC_CODEC_STATUS)

00000000h

Page 238

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