Data Sheet G14309EJ2V0DS00

15

µµµµPC1909

3.3 Overcurrent Limitation Operation

The internal configuration of the overcurrent latch circuit is shown in Figure 3-3 below.

Figure 3-3.

µµµµPC1909 Overcurrent Latch Circuit

VTH(OC)

To output circuit of OUT1

OC

CT

To PWM comparator 2

4

16

3 V

SQ

R

Overcurrent detection comparator

Flip-flop

If a voltage that exceeds the overcurrent detection voltage (VTH(OC) = 210 mV TYP.) is input to the OC pin, OUT1 is

latched to low level, and then OUT2 is latched to high level. The time between the detection of overcurrent and when

OUT1 becomes low level is the overcurrent detection delay time. Moreover, if the voltage of the CT pin exceeds 3.0 V, the

reset signal will be input to the flip-flop, and the latch status of OUT1 and OUT2 will be reset. When the OC pin voltage

reaches the overcurrent detection voltage, even in the cycle in which the latch status was reset, the latch and reset

operations will be repeated. In other words, the pulse width is limited every cycle (pulse-by-pulse current limitation).

The waveforms when overcurrent limitation is operating are shown in Figure 3-4 below.

Figure 3-4. Waveforms When Overcurrent Limitation Is Operating

OUT1

OC

DTC1

FB

DTC2

OUT2

CT

dCT

Reset voltage (3 V)

T6

td(OC)

VTH(OC)