Data Sheet G14309EJ2V0DS00

27

µµµµPC1909

4.7 Overcurrent Limiter Settings

The OC pin in the

µPC1909 allows the realization of a pulse-by-pulse overcurrent limiter, whose configuration is shown

in Figure 4-11 below.

Figure 4-11.

µµµµPC1909 Overcurrent Limiter

GND

IB(OC)

VTH(OC)

CT

OC

OUT1

16

SQ

R

3

4

11

Main switch

Output circuit of OUT1

Threshold voltage (3 V TYP.)

Flip-flop

Overcurrent detection comparator

PWM comparator 1

If overcurrent is detected by the overcurrent detection comparator, OUT1 is latched to low level by the flip-flop.

Moreover, if the triangle wave generated by the oscillator and a voltage with a threshold value that causes the output

latch to be reset are input to the other comparator the flip-flop will be reset at each cycle.

Because the reset threshold voltage is internally set to 3 V TYP. (about 75% VREF), if a maximum duty of 75% or over is

set by the DTC1 pin thus activating overcurrent limitation by the OC pin, two pulses will be inadvertently output in one

cycle. To allow for differences in ICs, do not set the maximum duty of DTC1 (60% or over) to more than 65% when

applying overcurrent limitation using the OC pin. Alternatively, do not use OC pin overcurrent limitation if setting the

maximum duty (60% or over) to more than 65%. In this case (overcurrent limitation current not used), connect the OC pin

directly to GND.

Discharge current flows through the OC pin. This discharge current is expressed as the input bias current of the

overcurrent latch block (IB(OC)). Although a filter is attached to the OC pin to prevent the overcurrent latch circuit from

malfunctioning due to the surge current that flows when the power MOS FET is turned on, be sure to set the resistor to

no more than 100

Ω to stop IB(OC) causing a shift in the overcurrent detection point.

When overcurrent is being limited by the OC pin, OUT1 operates at the minimum pulse width limitable by the

overcurrent latch circuit. The minimum pulse width is the sum of the

µPC1909’s overcurrent detection delay time (td(OC)),

the delay of the filter attached to the OC pin, and the turn-on time of the power MOS FET.

During steady operation (DTC2 < FB < DTC1), OUT2 operates at the duty determined by the FB voltage. Because the

FB voltage rises when the output of the converter drops, the duty of the OUT2 output drops in line with the converter

output, until it reaches the minimum duty set by the DTC1 voltage.