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LPC804 датащи(PDF) 14 Page - NXP Semiconductors |
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LPC804 датащи(HTML) 14 Page - NXP Semiconductors |
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14 / 89 page ![]() LPC804 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2023. All rights reserved. Product data sheet Rev. 2.1 — 25 July 2023 14 of 87 NXP Semiconductors LPC804 32-bit Arm Cortex-M0+ microcontroller [1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 15.5 “Pin states in different power modes”. For termination on unused pins, see Section 15.4 “Termination of unused pins”. [2] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [5] See Figure 16 for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is not available in deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from deep power-down mode. [6] The WKTCLKIN function is enabled in the PINENABLE0 register in the PMU. See the LPC804 user manual. [7] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is disabled. [8] Thermal pad for HVQFN33. VDD 18 18 15 20 B4 - - If VDDIO is present, VDD is the supply voltage for the I/Os on the right side of the package and the core voltage regulator. If VDDIO is not present, VDD also supplies voltage to the I/Os on the left side of the package. VDDIO - 3 - - - - - If present, it is the supply voltage for the I/Os on the left side of the package. VSS 19 16 33[8] C4 - - Ground. Table 4. Pin description Symbol Reset state[1] Type Description |
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