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CS4350 датащи(PDF) 33 Page - Cirrus Logic

номер детали CS4350
подробное описание детали  192 kHz Stereo DAC with Integrated PLL
PDF  39 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4350 датащи(HTML) 33 Page - Cirrus Logic

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33
CS4350
8.6.2
Soft Volume Ramp-Up after Error (RMP_UP) Bit 5
Function:
When set to 1 (default), an un-mute will be performed after executing a filter mode change, after LRCK is
lost, and after changing the Functional Mode. This un-mute is affected, similar to attenuation changes, by
the Soft and Zero Cross bits in the Volume and Mixing Control register.
When set to 0, an immediate un-mute is performed in these instances.
Note:
For best results, it is recommended that this feature be used in conjunction with the RMP_DN bit.
8.6.3
Soft Ramp-Down before Filter Mode Change (RMP_DN) Bit 4
Function:
When set to 1 (default), a mute will be performed prior to executing a filter mode change. This mute is
affected, similar to attenuation changes, by the Soft and Zero Cross bits in the Volume and Mixing Control
register.
When set to 0, an immediate mute is performed prior to executing a filter mode change.
Note:
For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.
8.6.4
Interpolation Filter Select (FILT_SEL) Bit 2
Function:
When set to 0 (default), the Interpolation Filter has a fast roll off.
When set to 1, the Interpolation Filter has a slow roll off.
The specifications for each filter can be found in the ”Combined Interpolation & On-Chip Analog Filter Re-
sponse” on page 11, and response plots can be found in Figures 22 through 27.
8.7
Misc. Control - Register 08h
8.7.1
Power Down (PDN) Bit 7
Function:
When set to 1 the entire device will enter a low-power state and the contents of the control registers will
be retained. The power-down bit defaults to ‘0’ on power-up.
8.7.2
Freeze Controls (FREEZE) Bit 5
Function:
When set to 1, this function allows modifications to be made to the registers without the changes taking
effect until FREEZE is set back to 0. To make multiple changes in the Control Port registers take effect
simultaneously, enable the FREEZE bit, make all register changes, then disable the FREEZE bit.
When set to 0 (default), register changes take effect immediately.
7
6
5
432
10
PDN
Reserved
FREEZE
POPG_EN
RMCK_CTRL1 RMCK_CTRL0 R_SELECT1
R_SELECT0
0
0
0
100
00



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