28

DS691A3

CS4350

8. REGISTER DESCRIPTION

** All register access is R/W unless specified otherwise**

8.1

Chip ID - Register 01h

Function:

This register is Read-Only. Bits 7 through 3 are the part number ID which is 11110b and the remaining Bits

(2 through 0) are for the chip revision (Rev. A0 = 000)

8.2

Mode Control - Register 02h

8.2.1

Digital Interface Format (DIF[2:0]) Bits 6-4

Function:

These bits select the interface format for the serial audio input.

The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital

Interface Format and the options are detailed in Figures 8-10.

8.2.2

De-Emphasis Control (DEM[1:0]) Bits 3-2

Default = 0

00 - No De-emphasis

01 - 44.1 kHz De-emphasis

10 - 48 kHz De-emphasis

11 - 32 kHz De-emphasis

Function:

Selects the appropriate digital filter to maintain the standard

15

µs/50 µs digital de-emphasis filter response at 32, 44.1

or 48 kHz sample rates. (See Figure 18)

Note:

De-emphasis is only available in Single-Speed

Mode

76

543

21

0

PART4

PART3

PART2

PART1

PART0

REV2

REV1

REV0

11

110

-

-

-

76

543

21

0

Reserved

DIF2

DIF1

DIF0

DEM1

DEM0

FM1

FM0

00

000

00

0

DIF2

DIF1

DIF0

Description

Format

Figure

000

Left-Justified, up to 24-bit data

0

(Default)

8

001

I²S, up to 24-bit data

1

9

010

Right-Justified, 16-bit data

2

10

011

Right-Justified, 24-bit data

3

10

100

TDM slot 0

4

12

101

TDM slot 1

5

12

110

TDM slot 2

6

12

111

TDM slot 3

7

12

Table 4. Digital Interface Formats

Gain

dB

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1

F2

3.183 kHz

10.61 kHz

Figure 18. De-Emphasis Curve