CS4350 datasheet(14/39 Pages) CIRRUS

номер детали	CS4350

подробное описание детали	192 kHz Stereo DAC with Integrated PLL

PDF	39 Pages

Scroll/Zoom	100%

производитель	CIRRUS [Cirrus Logic]

домашняя страница	http://www.cirrus.com

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14 / 39 page

DS691A3

CS4350

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VLC, CL =20pF)

Notes:

tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

10. Data must be held for sufficient time to bridge the transition time of CCLK.

11. For FSCK < 1 MHz.

12. CDOUT should not be sampled during this time.

Figure 6. Control Port Timing - SPI Mode

Parameter

Symbol

Min

Max

Unit

CCLK Clock Frequency

fsclk

-6

MHz

RST Rising Edge to CS Falling

tsrs

500

CCLK Edge to CS Falling (Note 9)

tspi

500

CS High Time Between Transmissions

tcsh

1.0

µs

CS Falling to CCLK Edge

tcss

CCLK Low Time

tscl

CCLK High Time

tsch

CDIN to CCLK Rising Setup Time

tdsu

CCLK Rising to DATA Hold Time (Note 10)

tdh

Rise Time of CCLK and CDIN (Note 11)

tr2

100

Fall Time of CCLK and CDIN (Note 11)

tf2

100

Transition Time from CCLK to CDOUT Valid (Note 12)

tr2

100

Time from CS rising to CDOUT High-Z

tf2

100

t r2

t f2

t dsu t dh

t sch

t scl

CCLK

CDIN

t css

t csh

t spi

t srs

RST

CDOUT

scdov

t cscdo

Hi-Im pedance

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