AD9396SLASHPCB datasheet(20/48 Pages) AD

20 / 48 page

AD9396

Rev. 0 | Page 20 of 48

The functional diagram for a single channel of the CSC, as

shown in Figure 13, is repeated for the remaining G and B

channels. The coefficients for these channels are b1, b2, b3, b4,

c1, c2, c3, and c4.

A programming example and register settings for several

common conversions are listed in the Color Space Converter

(CSC) Common Settings.

For a detailed functional description and more programming

examples, refer to the application note AN-795, AD9880 Color

Space Converter User's Guide.

TIMING DIAGRAMS

The following timing diagrams show the operation of the

AD9396.The output data clock signal is created so that its rising

edge always occurs between data transitions and can be used to

latch the output data externally. There is a pipeline in the

AD9396, which must be flushed before valid data becomes

available. This means six data sets are presented before valid

data is available.

×2

a1[12:0]

a2[12:0]

a3[12:0]

RIN [11:0]

BIN [11:0]

GIN [11:0]

×4

CSC_Mode[1:0]

a4[12:0]

ROUT [11:0]

4096

Figure 13. Single CSC Channel

DATAIN

P10

P11

HSIN

DATACK

8 CLOCK CYCLE DELAYS

DATAOUT

2 CLOCK CYCLE DELAYS

HSOUT

Figure 14. RGB ADC Timing

DATAIN

P10

P11

HSIN

DATACK

8 CLOCK CYCLE DELAYS

CB/CROUT

YOUT

2 CLOCK CYCLE DELAYS

NOTES:

1. PIXEL AFTER HSOUT CORRESPONDS TO BLUE INPUT.

2. EVEN NUMBER OF PIXEL DELAYS BETWEEN HSOUT AND DATAOUT.

HSOUT

Figure 15. YCrCb ADC Timing

Table 11.

Port

Red

Green

Blue

Bit

4:4:4

Red/Cr [7:0]

Green/Y [7:0]

Blue/Cb [7:0]

4:2:2

CbCr [7:0]

Y [7:0]

DDR 4:2:2 ↑ CbCr ↓ Y, Y

DDR ↑ 1 G [3:0]

DDR ↑ B [7:4]

DDR ↑ B [3:0]

DDR 4:2:2 ↑ CbCr [11:0]

4:4:4 DDR

DDR ↓ R [7:0]

DDR ↓ G [7:4]

DDR 4:2:2 ↓ Y,Y [11:0]

4:2:2 to 12

CbCr [11:0]

Y [11:0]

1 Arrows in the table indicate clock edge. Rising edge of clock =

↑, falling edge = ↓.

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