AD9396SLASHPCB datasheet(32/48 Pages) AD

32 / 48 page

AD9396

Rev. 0 | Page 32 of 48

0x15—Bit[5] VSYNC0 Detection Bit

Indicates if VSYNC0 is active. This bit is used to indicate when

activity is detected on the VSYNC0 input pin. If VSYNC is held

high or low, activity is not detected. The sync processing block

diagram shows where this function is implemented. 0 =

VSYNC0 not active. 1 = VSYNC0 is active.

0x15—Bit[4] VSYNC1 Detection Bit

Indicates if VSYNC1 is active. This bit is used to indicate when

activity is detected on the VSYNC1 input pin. If VSYNC is held

high or low, activity is not detected. The sync processing block

diagram shows where this function is implemented. 0 =

VSYNC1 not active. 1 = VSYNC1 is active.

0x15—Bit[3] SOG0 Detection Bit

Indicates if SOG0 is active. This bit is used to indicate when

activity is detected on the SOG0 input pin. If SOG is held high

or low, activity is not detected. The sync processing block

diagram shows where this function is implemented. 0 = SOG0

not active. 1 = SOG0 is active.

0x15—Bit[2] SOG1 Detection Bit

Indicates if SOG1 is active. This bit is used to indicate when

activity is detected on the SOG1 input pin. If SOG is held high

or low, activity is not detected. The sync processing block

diagram shows where this function is implemented. 0 = SOG1

not active. 1 = SOG1 is active.

0x15—Bit[1] Coast Detection Bit

This bit detects activity on the EXTCLK/EXTCOAST pin. It

indicates that one of the two signals is active, but it doesn’t

indicate if it is EXTCLK or COAST. A dc signal is not detected.

0 = no activity detected. 1 = activity detected.

POLARITY STATUS

0x16—Bit[7] HSYNC 0 Polarity

Indicates the polarity of the HSYNC0 input. 0 = HSYNC

polarity negative. 1 = HSYNC polarity positive.

0x16—Bit[6] HSYNC 1 Polarity

Indicates the polarity of the HSYNC1 input. 0 = HSYNC

polarity negative. 1 = HSYNC polarity positive.

0x16—Bit[5] VSYNC 0 Polarity

Indicates the polarity of the VSYNC0 input. 0 = VSYNC

polarity negative. 1 = VSYNC polarity positive.

0x16—Bit[4] VSYNC1 Polarity

Indicates the polarity of the VSYNC1 input. 0 = VSYNC

polarity negative. 1 = VSYNC polarity positive.

0x16—Bit[3] Coast Polarity

Indicates the polarity of the external coast signal. 0 = coast

polarity negative. 1 = coast polarity positive.

0x16—Bit[2] Pseudo Sync Detected

0x16—Bit[1] Sync Filter Locked

Indicates whether sync filter is locked to periodic sync signals.

0 = sync filter locked to periodic sync signal. 1 = sync filter not

locked.

0x16—Bit[0] Bad Sync Detect

0x17—Bits[3:0] HSYNCs per VSYNC MSBs

The 4 MSBs of the 12-bit counter that reports the number of

HSYNCs/VSYNC on the active input. This is useful in

determining the mode and aids in setting the PLL divide ratio.

0x18—Bits[7:0] HSYNCs per VSYNC LSBs

The 8 LSBs of the 12-bit counter that reports the number of

HSYNCs/VSYNC on the active input.

0x19—Bits[7:0] Clamp Placement

Number of pixel clocks after the trailing edge of HSYNC to

begin clamp. The power-up default is 8.

0x1A—Bits[7:0] Clamp Duration

Number of pixel clocks to clamp. The power-up default is 0x14.

0x1B—Bits[7] Red Clamp Select

This bit selects whether the red channel is clamped to ground or

midscale. Ground clamping is used for red in RGB applications

and midscale clamping is used in YPrPb (YUV) applications.

0 = channel clamped to ground during clamping period. 1 =

channel clamped to midscale during clamping period. The

power-up default is 0.

0x1B—Bit[6] Green Clamp Select

This bit selects whether the green channel is clamped to ground

or midscale. Ground clamping is normally used for green in

RGB applications and YPrPb (YUV) applications. 0 = channel

clamped to ground during clamping period. 1 = channel

clamped to midscale during clamping period. The power-up

default is 0.

0x1B—Bit[5] Blue Clamp Select

This bit selects whether the blue channel is clamped to ground

or midscale. Ground clamping is used for blue in RGB

applications and midscale clamping is used in YPrPb (YUV)

applications. 0 = channel clamped to ground during clamping

period. 1 = channel clamped to midscale during clamping

period. The power-up default is 0.

0x1B—Bit[4] Clamp During Coast

This bit permits clamping to be disabled during coast because

video signals are generally not at a known back porch or

midscale position during coast. 0 = clamping during coast is

disabled. Clamping during coast is enabled. The power-up

default is 0.

AD9396/PCB датащи(PDF) 32 Page - Analog Devices

AD9396/PCB датащи(HTML) 32 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL