AD9396SLASHPCB datasheet(41/48 Pages) AD

41 / 48 page

AD9396

Rev. 0 | Page 41 of 48

PCB LAYOUT RECOMMENDATIONS

The AD9396 is a high precision, high speed analog device. To

achieve the maximum performance from the part, it is impor-

tant to have a well laid-out board. The following is a guide for

designing a board using the AD9396.

ANALOG INTERFACE INPUTS

Using the following layout techniques on the graphics inputs is

extremely important:

•

Minimize the trace length running into the graphics inputs

by placing the AD9396 as close as possible to the graphics

VGA connector. Long input trace lengths are undesirable,

because they pick up more noise from the board and other

external sources.

•

Place the 75 Ω termination resistors (see Figure 3) as close

to the AD9396 chip as possible. Any additional trace length

between the termination resistors and the input of the

AD9396 increases the magnitude of reflections, which

corrupts the graphics signal.

•

Use 75 Ω matched impedance traces. Trace impedances

other than 75 Ω also increase the chance of reflections.

The AD9396 has very high input bandwidth (300 MHz). While

this is desirable for acquiring a high resolution PC graphics

signal with fast edges, it means that it also captures any high

frequency noise present. Therefore, it is important to reduce the

amount of noise that is coupled to the inputs. Avoid running

any digital traces near the analog inputs.

Due to the high bandwidth of the AD9396, sometimes low-pass

filtering the analog inputs can help to reduce noise. For many

applications, filtering is unnecessary. Experiments have shown

that placing a series ferrite bead prior to the 75 Ω termination

resistor is helpful in filtering out excess noise. Specifically, the

part used was the Fair-Rite 2508051217Z0, but each application

may work best with a different bead value. Alternatively, placing

a 100 Ω to 120 Ω resistor between the 75 Ω termination resistor

and the input coupling capacitor can also be beneficial.

POWER SUPPLY BYPASSING

It is recommended to bypass each power supply pin with a

0.1 μF capacitor. The exception is when two or more supply

pins are adjacent to each other. For these groupings of

powers/grounds, it is only necessary to have one bypass

capacitor. The fundamental idea is to have a bypass capacitor

within about 0.5 cm of each power pin. Also, avoid placing the

capacitor on the opposite side of the PC board from the

AD9396, because that interposes resistive vias in the path.

The bypass capacitors should be physically located between the

power plane and the power pin. Current should flow from the

power plane to the capacitor to the power pin. Do not make the

power connection between the capacitor and the power pin.

Placing a via underneath the capacitor pads down to the power

plane is generally the best approach.

It is particularly important to maintain low noise and good

stability of PVDD (the clock generator supply). Abrupt changes

in PVDD can result in similarly abrupt changes in sampling clock

phase and frequency. This can be avoided by careful attention to

regulation, filtering, and bypassing. It is highly desirable to

provide separate regulated supplies for each of the analog

circuitry groups (VD and PVDD).

Some graphic controllers use substantially different levels of

power when active (during active picture time) and when idle

(during HSYNC and VSYNC periods). This can result in a

measurable change in the voltage supplied to the analog supply

regulator, which can in turn produce changes in the regulated

analog supply voltage. This can be mitigated by regulating the

analog supply, or at least PVDD, from a different, cleaner, power

source (for example, from a 12 V supply).

It is recommended to use a single ground plane for the entire

board. Experience has shown repeatedly that the noise perfor-

mance is the same or better with a single ground plane. Using

multiple ground planes can be detrimental because each

separate ground plane is smaller and long ground loops can

result.

When using separate ground planes is unavoidable, placing a

single ground plane under the AD9396 is recommended. The

location of the split should be at the receiver of the digital

outputs. In this case it is even more important to place com-

ponents wisely because the current loops are much longer,

(current takes the path of least resistance). An example of a

current loop is: power plane to AD9396 to digital output

trace to digital data receiver to digital ground plane to analog

ground plane .

PLL

Place the PLL loop filter components as close as possible to the

FILT pin.

Do not place any digital or other high frequency traces near

these components.

Use the values suggested in the data sheet with 10% tolerances

or less.

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