Nexperia

74LVC2G00

Dual 2-input NAND gate

6. Pinning information

6.1. Pinning

74LVC2G00

1A

VCC

1B

1Y

2Y

2B

GND

2A

001aab736

1

2

3

4

6

5

8

7

Fig. 4. Pin configuration SOT505-2 (TSSOP8) and

SOT765-1 (VSSOP8)

74LVC2G00

2B

1Y

VCC

2A

2Y

1B

1A

GND

001aab737

3

6

2

7

1

8

4

5

Transparent top view

Fig. 5. Pin configuration SOT833-1, SOT1089, SOT1116

and SOT1203 (XSON8)

001aae980

1B

2B

1A

2Y

1Y

2A

Transparent top view

3

6

1

5

7

2

terminal 1

index area

74LVC2G00

Fig. 6. Pin configuration SOT902-2 (XQFN8)

8

4

GND

VCC

aaa-023988

Transparent top view

74LVC2G00

1

2

3

1A

1B

2Y

7

6

5

1Y

2B

2A

Fig. 7. Pin configuration SOT1233-2 (X2SON8)

6.2. Pin description

Table 3. Pin description

Pin

Symbol

SOT505-2, SOT765-1, SOT833-1, SOT1089,

SOT1116, SOT1203 and SOT1233-2

SOT902-2

Description

1A, 2A

1, 5

7, 3

data input

1B, 2B

2, 6

6, 2

data input

GND

4

4

ground (0 V)

1Y, 2Y

7, 3

1, 5

data output

VCC

8

8

supply voltage

74LVC2G00

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Product data sheet

Rev. 16 — 20 June 2022

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