CS5305GDWR28 datasheet(30/33 Pages) ONSEMI

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CS5305

http://onsemi.com

External FET Driver

The CS5305 is designed such that an external FET driver

IC is required. The GATE pin outputs are designed to drive

a 100 pF load, and do not have sufficient drive capability to

directly drive the gates of switch FETs. The GATE outputs

have a typical output high voltage of 2.5 V, so the turn−on

threshold of the FET driver should be approximately 2 V.

The GATE outputs are also phased such that the FET driver

IC should turn on the topside n−channel FET when the

GATE output goes high. The bottom−side n−channel FET

should be on when the GATE output is below the FET driver

IC turn−on threshold.

Additionally, the CS5305 provides a signal called

DRVON that can be connected to the ENABLE pin of FET

drivers that offer an enable feature. If the FET driver’s

ENABLE input is high, the FET driver output is determined

by the GATE input, and the switch FETs are driven

according to the conditions described above. If the FET

driver’s ENABLE input is low, all switch FETs are turned

off and no current is conducted to the load. This DRVON

signal is a logic output from the CS5305. DRVON goes high

when all internal functions of the CS5305 are operating

correctly and the IC is not in fault mode. A table of the

DRVON logic may be found in the Theory of Operation

section.

Choosing a FET driver IC with an enable feature

significantly improves system reliability, since a faulty

module is essentially disconnected from the load.

SGND Resistor

The module−to−load interface and the number of modules

placed in parallel determine the value of RSGND. The

CS5305 is specified to operate correctly with up to 55 mV

dropped across the module connector. It is assumed that the

maximum current allowed to flow in this connection to the

load is 1 mA.

RSGND + 55 mV (1 mA N)

where:

N = the number of VRM modules to be paralleled.

If four modules are to be paralleled, each contributes a

maximum of 250 μA to this connection, and so,

RSGND + 55 mV 250 mA + 220 W

This component is placed to ensure the VRM module will

regulate correctly if the module VOUT(SENSE)− connection

to the load is opened.

Layout Considerations

Enhanced V2 performs best under dynamic load

conditions if current ramp is kept small. However, this may

lead to pulse−width jitter or pulse skipping, particularly as

the ambient noise level at the control circuit increases. This

is a complicated design trade−off that can not be

mathematically characterized, and it is crucial to have a

“quiet” layout. Following the design/layout guidelines

below will provide the best system performance. Refer to

Figure 50 for a layout example and to page 2 for the

associated schematic. Numbers in parentheses refer to IC

pin numbers. Component names refer to the reference

designators for the application schematic.

1.Noise across the PWM comparator inputs needs to be

low or pulse width jitter will occur. Referring to the

block diagram, the CSREF pin (7) and the COMP pin

(14) present external information to the PWM

comparator. Any differential signal across these pins

is expressed directly across the PWM comparator,

which may cause pulse−width jitter or pulse skipping.

The solution is to provide a dedicated Kelvin

connection for sensing the VRM’s VOUT−. The IC’s

GND pin (28) and COMP capacitance need a

dedicated sense line to VOUT−, in effect making the IC

and COMP capacitance VOUT−ground−referenced.

This is desirable since the fast feedback path through

CSREF is connected to VOUT+ and is therefore also

VOUT−ground−referenced. Furthermore, a ground

strip under the IC is desirable since the COMP pin is

located at the opposite corner of the IC from the GND

pin. This ground strip further reduces the ambient

noise level of the CS5305 along with providing a

good connection from COMP return to GND and

VOUT−. Following this guideline will provide the

most system improvement from a layout standpoint.

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