BT261 datasheet(30/56 Pages) ETC

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Brooktree®

L261_H

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

INTERNAL REGISTERS

Command Register_3

This command register may be written to or read by the MPU at any time and is not initialized. CR30 corresponds to D0

and is the least signiﬁcant bit.

VSYNC Sample Register

This 8-bit register speciﬁes the number of pixel clock cycles after the falling edge of nongated CSYNC* at which to

sample the CSYNC* signal each scan line. By doing this, two samples per line will be taken during the vertical in-

terval when half-line pulses are present. The FIELD gate is programmed with the horizontal counter values (which

use only noise-gated CSYNC*); when sampling of the input sync occurs, VSYNC will toggle one half-line earlier at

the beginning of ﬁeld two as opposed to the beginning of ﬁeld one. This register may be written to or read by the MPU

at any time and is not initialized. Values from $00 (1) to $FF (256) may be speciﬁed. A value of 1/8 HCOUNT is rec-

ommended (~8

µs for the 15.75 KHz line-rate video). This is different from the 1/4 and 3/4 HCOUNT required for

FIELD-gate start and stop values, and greater than the 5

µs maximum width of sync pulses. For a conventional video

input with negative-going syncs, this produces a negative-going VSYNC* at the number of clock cycles speciﬁed af-

ter the falling CSYNC* edge. There is a 3-pixel-clock pipeline delay in clearing the horizontal counter when the part

is used in phase-lock loop mode. When the pixel clock is generated by dividing down an external oscillator, this delay

is in oscillator clocks. Thus, the output of this signal with respect to CSYNC* may be delayed (see Figure 8).

OSC Count Low and High Registers

These two 4-bit registers specify the number of rising and falling edges of an OSC input the pixel clock output

(CLOCK) is to be low and high. Values from $02 (2) to $OE (15) may be speciﬁed. These registers may be written

to or read by the MPU at any time and are not initialized. A value of $00 results in no pixel clock generation while

the OSC inputs are used. The counters clock on both the rising and falling edge of the selected OSC input. For exam-

ple, values of 4, 4 in OSC count low and high would result in a pixel clock with one fourth the frequency of the os-

cillator.

CR37, CR30

Phase lock line count

(0000 0000)

1 scan line

(0000 0001)

2 scan lines

(1111 1111)

256 scan lines

These bits specify the number of consecutive scan lines for

which lock must be maintained. If lock is not maintained for

the speciﬁed number of scan lines, the phase limiter is dis-

abled only if command bit CR22 is a logical one. SR05 is set

to zero if lock is maintained for the speciﬁed number of scan

lines.

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