BT261 datasheet(21/56 Pages) ETC

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CIRCUIT DESCRIPTION

The Status Registers SR00 and SR05 Used in Automatic Phase

L261_H

Bt261

30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller

The Status Registers SR00 and SR05 Used in

Automatic Phase Limiting

Bits 0 and 5 of the status register can be used to debug phase-locked-loop operation

of the Bt261. Phase-lock pixel-count bits CR27–CR24 deﬁne a pixel count used by

the Bt261 to determine if the part is in “Lock.” The Bt261 compares the time dur-

ing which the phase comparator is active (the PLL correction time) with the time

deﬁned in pixel count. If the compare time is less than phase-lock pixel count, the

loop is considered locked and SR00 is not altered. If the compare time is greater

than the phase-lock pixel count, SR00 is reset to zero. Previous to query, SR00

must be set to one by writing to command bit CR12.

CR37–CR30 contains the phase-lock line count. This register determines the

number of lines that must have a phase error less than that deﬁned in the

CR27–CR24 phase-lock pixel count for the system to be considered continuously

locked. SR05 is reset to zero if there have been phase-lock line-count number of

continuous lines with phase error less than that deﬁned in the phase-lock pixel

count. SR05 cannot be altered by the MPU. SR05 is set to one if SR00 is set to zero

on any line (indicating a phase error greater than that deﬁned in phase-lock pixel

count).

Bit 5 of the status register is used by the phase-limiting circuitry to determine if

phase limiting should be enabled or disabled. If phase limiting is automatic, i.e.,

when phase limiting is enabled and lock is not overridden, (CR10 = CR22 = 1),

SR05 determines whether phase limiting should be performed. SR05 is the lock

control indicated in Figure 3a.

The active period compared with the value in CR27–CR24 is output directly

from the phase comparator. Because of this, all digital noise-gate and phase-limit

operation is included when the phase error is compared with the phase-lock pix-

el-count value. Therefore, the value in CR27–CR24 must be less than 500 ns in the

typical case or 350 ns in the worst case commercial temperature range. This re-

quirement ensures that a phase-limited line is not incorrectly interpreted as a

locked line.

SR05 can be used as a PLL debug tool. If the status register is addressed and the

RD* pin of the Bt261 is held low, then SR05 will indicate the lock status. This bit

will set low when lock is held for the number of lines deﬁned in the phase-lock line

count. When this condition is observed while the phase-comparator output is

viewed through two vertical intervals, the Bt261 response relative to the loop per-

formance can be studied. Lock should be indicated well before the next vertical in-

terval (see Figure 6). Phase-limit enable must be deactivated during this evaluation

(CR10 = 0); otherwise, phase limiting will affect the ability to monitor the loop-ac-

quisition time.

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