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DSPIC30F датащи(PDF) 147 Page - Microchip Technology |
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DSPIC30F датащи(HTML) 147 Page - Microchip Technology |
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147 / 220 page ![]() 2004 Microchip Technology Inc. Preliminary DS70116C-page 145 dsPIC30F5011/5013 Table 20-6 shows a second example of the bit conditions for the RCON register. In this case, it is not assumed the user has set/cleared specific bits prior to action specified in the condition column. TABLE 20-6: INITIALIZATION CONDITION FOR RCON REGISTER: CASE 2 Condition Program Counter TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR Power-on Reset 0x000000 00 0 0 0 0 0 1 1 Brown-out Reset 0x000000 uu u u u u u 0 1 MCLR Reset during normal operation 0x000000 uu 1 0 0 0 0 u u Software Reset during normal operation 0x000000 uu 0 1 0 0 0 u u MCLR Reset during Sleep 0x000000 uu 1 u 0 0 1 u u MCLR Reset during Idle 0x000000 uu 1 u 0 1 0 u u WDT Time-out Reset 0x000000 uu 0 0 1 0 0 u u WDT Wake-up PC + 2 uu u u 1 u 1 u u Interrupt Wake-up from Sleep PC + 2(1) uu u u u u 1 u u Clock Failure Trap 0x000004 uu u u u u u u u Trap Reset 0x000000 1u u u u u u u u Illegal Operation Reset 0x000000 u1 u u u u u u u Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. |
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