DSPIC30F datasheet(59/220 Pages) MICROCHIP

59 / 220 page

 2004 Microchip Technology Inc.

Preliminary

DS70116C-page 57

dsPIC30F5011/5013

8.0

I/O PORTS

All of the device pins (except VDD, VSS, MCLR and

OSC1/CLKI) are shared between the peripherals and

the parallel I/O ports.

All I/O input ports feature Schmitt Trigger inputs for

improved noise immunity.

8.1

Parallel I/O (PIO) Ports

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as

a general purpose output pin is disabled. The I/O pin

may be read but the output driver for the parallel port bit

will be disabled. If a peripheral is enabled but the

peripheral is not actively driving a pin, that pin may be

driven by a port.

All port pins have three registers directly associated

with the operation of the port pin. The Data Direction

or an output. If the data direction bit is a ‘1’, then the pin

is an input. All port pins are defined as inputs after a

Reset. Reads from the latch (LATx), read the latch.

Writes to the latch, write the latch (LATx). Reads from

the port (PORTx), read the port pins and writes to the

port pins, write the latch (LATx).

Any bit and its associated data and control registers

that are not valid for a particular device will be dis-

abled. That means the corresponding LATx and TRISx

registers and the port pin will read as zeros.

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs. An example is the

INT4 pin.

The format of the registers for PORTA are shown in

Table 8-1.

The TRISA (Data Direction Control) register controls

the direction of the RA<7:0> pins, as well as the INTx

pins and the VREF pins. The LATA register supplies

data to the outputs and is readable/writable. Reading

the PORTA register yields the state of the input pins,

while writing the PORTA register modifies the contents

of the LATA register.

A parallel I/O (PIO) port that shares a pin with a periph-

eral is, in general, subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

has ownership of the output data and control signals of

the I/O pad cell. Figure 8-2 shows how ports are shared

with other peripherals and the associated I/O cell (pad)

to which they are connected. Table 8-2 through

Table 8-9 show the formats of the registers for the

shared ports, PORTB through PORTG.

FIGURE 8-1:

BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE

Note:

The actual bits in use vary between

devices.

WR LAT +

TRIS Latch

I/O Pad

WR Port

Data Bus

Data Latch

Read LAT

Read Port

Read TRIS

WR TRIS

I/O Cell

Dedicated Port Module

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