ICS1893BFILF datasheet(77/133 Pages) RENESAS

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Chapter 7 Management Register Set

ICS1893BF, Rev. F, 5/13/10

May, 2010

ICS1893BF Data Sheet Rev. F - Release

7.11.1 Command Override Write Enable (bit 16.15)

The Command Override Write Enable bit provides an STA the ability to alter the Command Override Write

(CW) bits located throughout the MII Register set. A two-step process is required to alter the value of a CW

bit:

1. Step one is to issue a Command Override Write, (that is, set bit 16.15 to logic one). This step enables

the next MDIO write to have the ability to alter any CW bit.

2. Step two is to write to the register that includes the CW bit which requires modification.

Note: The Command Override Write Enable bit is a Self-Clearing bit that is automatically reset to logic

zero after the next MII write, thereby allowing only one subsequent write to alter the CW bits in a

single register. To alter additional CW bits, the Command Override Write Enable bit must once

again be set to logic one.

7.11.2 ICS Reserved (bits 16.14:11)

IDT is reserving these bits for future use. Functionally, these bits are equivalent to IEEE Reserved bits.

When one of these reserved bits is:

• Read by an STA, the ICS1893BF returns a logic zero.

• Written to by an STA, the STA must use the default value specified in this data sheet.

IDT uses some reserved bits to invoke auxiliary functions. To ensure proper operation of the ICS1893BF,

an STA must maintain the default value of these bits. Therefore, IDT recommends that an STA always write

the default value of any reserved bits during all management register write operations.

7.11.3 PHY Address (bits 16.10:6)

These five bits hold the Serial Management Port Address of the ICS1893BF. During either a hardware reset

or a power-on reset, the PHY address is read from the LED interface. (For information on the LED

interface, see Section 5.5, “Status Interface” and Section 8.2.2, “Multi-Function (Multiplexed) Pins: PHY

Address and LED Pins”). The PHY address is then latched into this register. (The value of each of the PHY

Address bits is unaffected by a software reset.)

7.11.4 Stream Cipher Scrambler Test Mode (bit 16.5)

The Stream Cipher Scrambler Test Mode bit is used to force the ICS1893BF to lose LOCK, thereby

requiring the Stream Cipher Scrambler to resynchronize.

7.11.5 ICS Reserved (bit 16.4)

See Section 7.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.

7.11.6 NRZ/NRZI Encoding (bit 16.3)

This bit allows an STA to control whether NRZ (Not Return to Zero) or NRZI (Not Return to Zero, Invert on

One) encoding is applied to the serial transmit data stream in 100Base-TX mode. When this bit is logic:

• Zero, the ICS1893BF encodes the serial transmit data stream using NRZ encoding.

• One, the ICS1893BF encodes the serial transmit data stream using NRZI encoding.

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