ICS1893BFILF datasheet(55/133 Pages) RENESAS

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Chapter 7 Management Register Set

ICS1893BF, Rev. F, 5/13/10

May, 2010

ICS1893BF Data Sheet Rev. F - Release

7.2.5 Low Power Mode (bit 0.11)

This bit provides one way to control the ICS1893BF low-power mode function. When bit 0.11 is logic:

• Zero, there is no impact to ICS1893BF operations.

• One, the ICS1893BF enters the low-power mode. In this case, the ICS1893BF disables all internal

functions and drives all MAC output pins low except for those that support the MII Serial Management

Port. In addition, the ICS1893BF internally activates the TPTRI function to tri-state the signals on the

Twisted-Pair Transmit pins (TP_TXP and TP_TXN) and achieve additional power savings.

Note: There are two ways the ICS1893BF can enter low-power mode. When entering low-power mode:

• By setting bit 0.11 to logic one, the ICS1893BF maintains the value of all Management Register

bits except the latching high (LH) and latching low (LL) status bits, which are re-initialized to their

default values instead. (For more information on latching high and latching low bits, see Section

7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)

• During a reset, the ICS1893BF sets all management register bits to their default values.

7.2.6 Isolate (bit 0.10)

This bit controls the ICS1893BF Isolate function. When bit 0.10 is logic:

• Zero, there is no impact to ICS1893BF operations.

• One, the ICS1893BF electrically isolates its data paths from the MAC Interface. The ICS1893BF places

all MAC output signals (TXCLK, RXCLK, RXDV, RXER, RXD[3:0], COL, and CRS) in a high-impedance

state and it isolates all MAC input signals (TXD[3:0], TXEN, and TXER). In this mode, the Serial

Management Interface continues to operate normally (that is, bit 0.10 does not affect the Management

Interface).

The default value for bit 0.10 depends upon the PHY address of Table 7-16. If the PHY address:

• Is equal to 00000b, then the default value of bit 0.10 is logic one, and the ICS1893BF isolates itself from

the MAC Interface.

• Is not equal to 00000b, then the default value of bit 0.10 is logic zero, and the ICS1893BF does not

isolate its MAC Interface.

7.2.7 Restart Auto-Negotiation (bit 0.9)

This bit allows an STA to restart the auto-negotiation process in Software mode (that is, the HW/SW pin is

logic one). When bit 0.12 is logic:

• Zero, the Auto-Negotiation sublayer is disabled, and the ICS1893BF isolates any attempt by the STA to

set bit 0.9 to logic one.

• One (as set by an STA), the ICS1893BF restarts the auto-negotiation process. Once the auto-negotiation

process begins, the ICS1893BF automatically sets this bit to logic zero, thereby providing the

self-clearing feature.

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