MMPF0100Z datasheet(7/128 Pages) NXP

7 / 128 page

NXP Semiconductors

PF0100Z

PIN CONNECTIONS

3.2

Pin definitions

Table 3. PF0100Z pin definitions

Pin number

Pin name

function

Max rating

Type

Definition

INTB

3.6 V

Digital

Open drain interrupt signal to processor

SDWNB

3.6 V

Digital

Open drain signal to indicate an imminent system shutdown

RESETBMCU

3.6 V

Digital

Open drain reset output to processor. Alternatively can be used as a power

good output.

STANDBY

3.6 V

Digital

Standby input signal from processor

5ICTEST

7.5 V

Digital/

Analog

Reserved pin. Connect to GND in application.

6SW1FB (5)

3.6 V

Analog

Output voltage feedback for SW1A/B. Route this trace separately from the

high current path and terminate at the output capacitance.

7SW1AIN (5)

4.8 V

Analog

Input to SW1A regulator. Bypass with at least a 4.7

F ceramic capacitor

and a 0.1

F decoupling capacitor as close to the pin as possible.

SW1ALX (5)

4.8 V

Analog

Regulator 1A switch node connection

SW1BLX (5)

4.8 V

Analog

Regulator 1B switch node connection

SW1BIN (5)

4.8 V

Analog

Input to SW1B regulator. Bypass with at least a 4.7

F ceramic capacitor

and a 0.1

F decoupling capacitor as close to the pin as possible.

SW1CLX (5)

4.8 V

Analog

Regulator 1C switch node connection

SW1CIN (5)

4.8 V

Analog

Input to SW1C regulator. Bypass with at least a 4.7

F ceramic capacitor

and a 0.1

F decoupling capacitor as close to the pin as possible.

SW1CFB (5)

3.6V

Analog

Output voltage feedback for SW1C. Route this trace separately from the

high current path and terminate at the output capacitance.

SW1VSSSNS

GND

Ground reference for regulators SW1ABC. It is connected externally to

GNDREF through a board ground plane.

GNDREF1

GND

Ground reference for regulators SW2 and SW4. It is connected externally to

GNDREF, via board ground plane.

VGEN1

2.5 V

Analog

VGEN1 regulator output, Bypass with a 2.2

F ceramic output capacitor.

VIN1

3.6 V

Analog

VGEN1, 2 input supply. Bypass with a 1.0

F decoupling capacitor as close

to the pin as possible.

VGEN2

2.5 V

Analog

VGEN2 regulator output, Bypass with a 4.7

F ceramic output capacitor.

SW4FB (5)

3.6 V

Analog

Output voltage feedback for SW4. Route this trace separately from the high

current path and terminate at the output capacitance.

SW4IN (5)

4.8 V

Analog

Input to SW4 regulator. Bypass with at least a 4.7

F ceramic capacitor and

a 0.1

F decoupling capacitor as close to the pin as possible.

SW4LX (5)

4.8 V

Analog

Regulator 4 switch node connection

SW2LX (5)

4.8 V

Analog

Regulator 2 switch node connection

SW2IN (5)

4.8 V

Analog

Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with

at least a 4.7

F ceramic capacitor and a 0.1 F decoupling capacitor as

close to these pins as possible.

SW2IN (5)

4.8 V

Analog

SW2FB (5)

3.6 V

Analog

Output voltage feedback for SW2. Route this trace separately from the high

current path and terminate at the output capacitance.

VGEN3

3.6 V

Analog

VGEN3 regulator output. Bypass with a 2.2

F ceramic output capacitor.

VIN2

3.6 V

Analog

VGEN3,4 input. Bypass with a 1.0

F decoupling capacitor as close to the

pin as possible.

VGEN4

3.6 V

Analog

VGEN4 regulator output, Bypass with a 4.7

F ceramic output capacitor.

VHALF

3.6 V

Analog

Half supply reference for VREFDDR

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