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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7260 датащи(PDF) 99 Page - STMicroelectronics |
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ST7260 датащи(HTML) 99 Page - STMicroelectronics |
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99 / 117 page  ST7260 99/117 13.9 CONTROL PIN CHARACTERISTICS 13.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Notes: 1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 2. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2 and the sum of IIO (I/ O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistive transistor. This data is based on characterization results, not tested in production. 4. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIH Input High Level Voltage 0.7xVDD VDD V VIL Input Low Voltage VSS 0.3xVDD V Vhys Schmitt trigger voltage hysteresis 1) 400 mV VOL Output low level voltage 2) VDD=5V IIO=5 mA 0.8 V IIO=7.5 mA 1.3 RON Weak pull-up equivalent resistor 3) VIN=VSS VDD=5 V 50 80 100 k Ω tw(RSTL)out Generated reset pulse duration External pin or internal reset sources 6 30 1/fSFOSC µs th(RSTL)in External reset pulse hold time 4) 5 µs |
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