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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7260 датащи(PDF) 70 Page - STMicroelectronics |
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ST7260 датащи(HTML) 70 Page - STMicroelectronics |
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70 / 117 page  ST7260 70/117 SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (SCIDR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift reg- ister (see Figure 35). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 35). BAUD RATE REGISTER (SCIBRR) Read/Write Reset Value: 0000 0000 (00h) Bits 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: Bits 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock. Bits 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP[1:0] bits define the total division applied to the bus clock to yield the receive rate clock. 70 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 70 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 PR Prescaling factor SCP1 SCP0 10 0 30 1 41 0 13 1 1 TR dividing factor SCT2 SCT1 SCT0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 RR Dividing factor SCR2 SCR1 SCR0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 PR Prescaling factor SCP1 SCP0 |
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