PowerPC 603 RISC Microprocessor Technical Summary

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3.2.6 Segment Registers (SRs)

For memory management, 32-bit PowerPC microprocessors implement sixteen 32-bit segment registers

(SRs). To speed access, the 603 implements the segment registers as two arrays; a main array (for data

memory accesses) and a shadow array (for instruction memory accesses). Loading a segment entry with the

Move to Segment Register (mtsr) instruction loads both arrays.

3.2.7 Special-Purpose Registers (SPRs)

The PowerPC operating environment architecture defines numerous special-purpose registers that serve a

variety of functions, such as providing controls, indicating status, configuring the processor, and performing

special operations. During normal execution, a program can access the registers, shown in Figure 2,

depending on the program’s access privilege (supervisor or user, determined by the privilege-level (PR) bit

in the MSR). Note that registers such as the GPRs and FPRs are accessed through operands that are part of

the instructions. Access to registers can be explicit (that is, through the use of specific instructions for that

purpose such as Move to Special-Purpose Register (mtspr) and Move from Special-Purpose Register

(mfspr) instructions) or implicit, as the part of the execution of an instruction. Some registers are accessed

both explicitly and implicitly

In the 603, all SPRs are 32 bits wide.

3.2.7.1 User-Level SPRs

The following 603 SPRs are accessible by user-level software:

•

Link register (LR)—The link register can be used to provide the branch target address and to hold

the return address after branch and link instructions. The LR is 32 bits wide in 32-bit

implementations.

•

Count register (CTR)—The CTR is decremented and tested automatically as a result of branch-and-

count instructions. The CTR is 32 bits wide in 32-bit implementations.

•

Integer exception register (XER)—The 32-bit XER contains the summary overflow bit, integer

carry bit, overflow bit, and a field specifying the number of bytes to be transferred by a Load String

Word Indexed (lswx) or Store String Word Indexed (stswx) instruction.

3.2.7.2 Supervisor-Level SPRs

The 603 also contains SPRs that can be accessed only by supervisor-level software. These registers consist

of the following:

•

The 32-bit DSISR defines the cause of data access and alignment exceptions.

•

The data address register (DAR) is a 32-bit register that holds the address of an access after an

alignment or DSI exception.

•

Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for

causing a decrementer exception after a programmable delay.

•

The 32-bit SDR1 specifies the page table format used in virtual-to-physical address translation for

pages. (Note that physical address is referred to as real address in the architecture specification.)

•

The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the 603 for

saving the address of the instruction that caused the exception, and the address to return to when a

Return from Interrupt (rfi) instruction is executed.

•

The machine status save/restore register 1 (SRR1) is a 32-bit register used to save machine status

on exceptions and to restore machine status when an rfi instruction is executed.

•

The 32-bit SPRG0–SPRG3 registers are provided for operating system use.

Freescale Semiconductor, Inc.

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