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PowerPC 603 RISC Microprocessor Technical Summary

Part 1 PowerPC 603 Microprocessor Overview

This section describes the features of the 603, provides a block diagram showing the major functional units,

and gives an overview of how the 603 operates.

The 603 is the first low-power implementation of the PowerPC microprocessor family of reduced instruction

set computer (RISC) microprocessors. The 603 implements the 32-bit portion of the PowerPC architecture,

which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and floating-point data

types of 32 and 64 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit

integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture.

The 603 provides four software controllable power-saving modes. Three of the modes (the nap, doze, and

sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor.

The fourth is a dynamic power management mode that causes the functional units in the 603 to

automatically enter a low-power mode when the functional units are idle without affecting operational

performance, software execution, or any external hardware.

The 603 is a superscalar processor capable of issuing and retiring as many as three instructions per clock.

Instructions can execute out of order for increased performance; however, the 603 makes completion appear

sequential.

The 603 integrates five execution units—an integer unit (IU), a floating-point unit (FPU), a branch

processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five

instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency

and throughput for 603-based systems. Most integer instructions execute in one clock cycle. The FPU is

pipelined so a single-precision multiply-add instruction can be issued every clock cycle.

The 603 provides independent on-chip, 8-Kbyte, two-way set-associative, physically addressed caches for

instructions and data and on-chip instruction and data memory management units (MMUs). The MMUs

contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and

ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block

translation. The TLBs and caches use a least recently used (LRU) replacement algorithm. The 603 also

supports block address translation through the use of two independent instruction and data block address

translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously

with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture,

if an effective address hits in both the TLB and BAT array, the BAT translation takes priority.

The 603 has a selectable 32- or 64-bit data bus and a 32-bit address bus. The 603 interface protocol allows

multiple masters to compete for system resources through a central external arbiter. The 603 provides a

three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol

is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates

coherently in systems that contain four-state caches. The 603 supports single-beat and burst data transfers

for memory accesses; it also supports both memory-mapped I/O and direct-store interface addressing.

The 603 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with

TTL devices.

1.1 PowerPC 603 Microprocessor Features

This section describes details of the 603’s implementation of the PowerPC architecture. Major features of

the 603 are as follows:

•

High-performance, superscalar microprocessor

— As many as three instructions issued and retired per clock

— As many as five instructions in execution per clock

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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