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PowerPC 603 RISC Microprocessor Technical Summary

Specific features of the 603 are listed in Section 1.1, “PowerPC 603 Microprocessor Features.”

3.2 PowerPC Registers and Programming Model

The PowerPC architecture defines register-to-register operations for most computational instructions.

Source operands for these instructions are accessed from the registers or are provided as immediate values

embedded in the instruction opcode. The three-register instruction format allows specification of a target

register distinct from the two source operands. Load and store instructions transfer data between registers

and memory.

PowerPC processors have two levels of privilege—supervisor mode of operation (typically used by the

operating system) and user mode of operation (used by the application software). The programming models

incorporate 32 GPRs, 32 FPRs, special-purpose registers (SPRs), and several miscellaneous registers. Each

PowerPC microprocessor also has its own unique set of hardware implementation (HID) registers.

Having access to privileged instructions, registers, and other resources allows the operating system to

control the application environment (providing virtual memory and protecting operating-system and critical

machine resources). Instructions that control the state of the processor, the address translation mechanism,

and supervisor registers can be executed only when the processor is operating in supervisor mode.

The following sections summarize the PowerPC registers that are implemented in the 603.

3.2.1 General-Purpose Registers (GPRs)

The PowerPC architecture defines 32 user-level, general-purpose registers (GPRs). These registers are either

32 bits wide in 32-bit PowerPC microprocessors and 64 bits wide in 64-bit PowerPC microprocessors. The

GPRs serve as the data source or destination for all integer instructions.

3.2.2 Floating-Point Registers (FPRs)

The PowerPC architecture also defines 32 user-level, 64-bit floating-point registers (FPRs). The FPRs serve

as the data source or destination for floating-point instructions. These registers can contain data objects of

either single- or double-precision floating-point formats.

3.2.3 Condition Register (CR)

The CR is a 32-bit user-level register that consists of eight four-bit fields that reflect the results of certain

operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and

provide a mechanism for testing and branching.

3.2.4 Floating-Point Status and Control Register (FPSCR)

The floating-point status and control register (FPSCR) is a user-level register that contains all exception

signal bits, exception summary bits, exception enable bits, and rounding control bits needed for compliance

with the IEEE 754 standard.

3.2.5 Machine State Register (MSR)

The machine state register (MSR) is a supervisor-level register that defines the state of the processor. The

contents of this register are saved when an exception is taken and restored when the exception handling

completes. The 603 implements the MSR as a 32-bit register; 64-bit PowerPC processors implement a 64-

bit MSR.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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