U6239B

TELEFUNKEN Semiconductors

Rev. A3, 28-May-97

2 (15)

Ordering Information

Extended Type Number

Package

Remarks

U6239B-AFPG3

SO16, plastic package

Taped and reeled

SSO16 package on request

Pin Configuration

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

RDS/AMS

SDA

95 10947

SCL

P7

P6/ ADC

P5

PD

Q1

RFi

RFi

P0/ Lock

AS/ENABLE/

P3

P4

VD

GND

Pin

Symbol

Function

1

PD

Charge pump output

2

Q1

Crystal input

3

RDS/

AMS

Reference divider select input

(3-wire bus mode)

Address mode select input

4

SDA

Data input/ output

5

SCL

Clock input

6

P7

Port 7 input/ output

7

P6/

ADC

Port 6 output

Analog-Digital-Converter input

8

P5

Port 5 input/ output

9

P4

Port 4 input/ output

10

AS/

ENABLE/

P3

Address select input

Enable input

Port 3 output

11

P0/Lock

Port 0 output/Lock output

12

Supply voltage

13

RFi

RF input

14

RFi

RF input

15

GND

Ground

16

VD

Active filter output

Circuit Description

The U6239B is a single-chip PLL designed for SAT TV

tuner and cable tuner. It consists of a divide-by-16

prescaler with an integrated preamplifier, a 15-bit

programmable divider, a crystal oscillator, and a

reference divider with selectable divider ratios, a phase/

frequency detector together with a charge pump which

drives the tuning amplifier. Only one external transistor

is required for varactor line driving. The device can be

detects automatically which bus format has been

received. Therefore, there is no need for a bus selection

depending on the voltage level at Pin 3. They are

programmed by applying a specific input voltage to the

address select input Pin 10, enabling the use of up to four

synthesizers in a system. If the fixed address is used, this

pin can be used as a normal output port. The same pin

serves as the enable signal input in 3-wire bus mode.

Depending whether the fixed address is used or not there

are five or six open collector outputs for switching

functions available. In 3-wire bus mode there are four

open collector outputs and one lock signal output. All

open collector outputs are capable of sinking at least

(ADC) is available for digital AFC (automatic frequency

control) applications and the ports P4, P5 and P7 can also

be used as input ports.