U6239B

TELEFUNKEN Semiconductors

Rev. A3, 28-May-97

7 (15)

Reference divider selection RD1, RD2, RD3:

RD3

RD2

RD1

Reference

Divider Ratio

Frequency

Step Size*

Max. Operating

Frequency*

1

1

1

1

0

0

1

1

0

1

0

1

1024

off

256

512

62.5 kHz

–

250 kHz

125 kHz

2.047 GHz

–

2.9 GHz

2.9 GHz

0

0

0

0

0

0

1

1

0

1

0

1

140

25

250

50

457.14 kHz

2560 kHz

256 kHz

1280 kHz

2.9 GHz

2.9 GHz

2.9 GHz

2.9 GHz

* when a 4MHz crystal is used

Address selection AS1, AS2, AMS:

AMS

Voltage at Pin 3

AS1

AS2

Address

Dec. Value

Voltage at Pin 10

< 0.8 V or open

< 0.8 V or open

< 0.8 V or open

< 0.8 V or open

0

0

1

1

0

1

0

1

C0

C2

C4

C6

192

194

196

198

always valid

> 2.4

> 2.4

> 2.4

> 2.4

0

0

1

1

0

1

0

1

C0

C2

C4

C6

192

194

196

198

open

Read Mode (Address byte LSB = 1)

After the address transmission (first byte), the status byte

can be read from the device on the SDA line (MSB first).

Data is valid on the SDA line during logic high of the SCL

signal. The controller accepting the data has to pull the

SDA line to low-level during all status-byte acknowledge

periods to read another status byte. If the controller fails

to pull the SDA line to low-level during this period, the

device will then release the SDA line to allow the

controller to generate a STOP condition.

The POR bit (power-on-reset) is set to a logic 1 when the

(at 25

°C) and also when the device is initially turned on.

The POR bit is reset to a logic 0 when the read sequence

is terminated by a STOP condition. When the POR bit is

programmed information is lost and the port outputs are

all set to high impedance state.

The FL bit indicates whether the loop is in phase lock

condition (logic 1) or not (logic 0).

If the ADC or the ports are to be used as inputs, the

corresponding outputs must be programmed to a high

impedance state (logic 1).

The bits I2, I1 and I0 show the status of the I/O ports P7,

P5 and P4 respectively. A logic 0 indicates a LOW level

and a logic 1 a HIGH level (TTL levels).

The bits A2, A1 and A0 represent the digital information

of the 5-level ADC. This converter can be used to feed

AFC information to the controller from the IF section of

the receiver, as shown in the typical application circuit on

page 14.