U6239B

TELEFUNKEN Semiconductors

Rev. A3, 28-May-97

9 (15)

SDA

SCL

t

t

t

tt

t

t

t

t

t

R

F

S STP

H DAT

S DAT

HIGH

LOW

S STT

W STT

H STT

START

CLOCK

DATACHANGE

STOP

9611812

Figure 2.

Parameters

Symbol

Min.

Max.

Unit

Rise time SDA, SCL

15

ms

Fall time SDA, SCL

15

ms

Clock frequency SCL

0

100

kHz

Clock ‘H’ pulse

1

ms

Clock ‘L’ pulse

1

ms

Hold time start

1

ms

Waiting time start

1

ms

Setup time start

1

ms

Setup time stop

1

ms

Setup time data

0.25

ms

Hold time data

0

ms

3-Wire Bus Description

When the U6239B is controlled via a 3-wire bus format,

then data, clock and enable signals are fed into the SDA,

SCL and AS/ENABLE/P3 lines respectively. The

diagram “3-wire bus pulse diagram” shows the data for-

mat. The data consist of a single word which contains the

programmable divider (14 bit) and port information. Bit

No. 15 of the programmable divider is always zero, when

the 3-wire bus mode is active. The data is only clocked

into the internal data shift register on the negative clock

transition during the enable high period. During enable

low periods the clock input is disabled. New data words

are only accepted by the internal data latches from the

shift register on a negative transition of the enable signal

if exactly eigtheen clock pulses were sent during the high

period of the enable. The data sequence and the timing is

described in the following diagrams.

In 3-wire bus mode Pin 9 automatically becomes the

lock-signal output. An improved lock detect circuit

generates a flag when the loop has attained lock. ‘In lock’

is indicated by a low impedance state (on) of the open

collector output.

In 3-wire bus mode the high charge pump current is

always active. The charge pump current can only be con-

The complete PLL function can be disabled by

programming a normally not used division ratio of zero.

This allows the tuner alignment by supplying the tuning

voltage directly through the 33 V supply voltage of the

tuner.

In 3-wire bus mode the division ratio of the reference

divider is controlled via information RD1, RD2 and the

reference divider select input Pin 3.