Datasheet

9-Feb-2022

CFR0011-120-01

Revision 1.04

Page 5 of 9

SLG55022-200030

High Voltage Gate Driver

©2022 Renesas Electronics Corporation

Delay Time and Slew Rates

The two components of controlling the application of FET source voltage to the load are a fixed time delay before beginning turn

on of the FET (DLY_t below) and the Slew Time of the source voltage (Slew_t below).

Having control over the Slew Rate of the FET’s source voltage as the FET is turning on is important in controlling dv/dt caused

transients. A power FET, for example, switching a 5 V rail which has a total of 500

µF of decoupling, fully on in 10 µs will generate

a 250 A current surge which is very undesirable. If the FET turn on time can be stretched to 1 ms, the current surge to charge

the decoupling capacitors is reduced to 2.5 A. The SLG55022 controls slew rate of a FET’s source voltage as it is turned on. A

range of slew rates are available as device order options. Obviously the time to fully slew the source voltage to fully on is a function

of the drain supply voltage. The table and graph below shows source voltage ramp times for various slew rates supported by the

SLG55022 for a range of specific source voltages.

* The minimum time that ON can be de-asserted between switching cycles is 100 ms.

Slew Rates

(V/ms)

Ramp Times (ms) vs. Source Voltages (V)

1.1 V

1.5 V

1.8 V

3.3 V

5.0 V

12 V

18.5 V

2.00

0.55

0.75

0.90

1.65

2.50

6.00

9.25

ON

V S

IS

DLY_t

Slew_t

Discharge_t

*